Timing-Driven Simulated Annealing for FPGA Placement in Neural Network Realization

Yu, Le; Guo, Baojin

doi:10.3390/electronics12173562

Cited by 2 publications

(1 citation statement)

References 19 publications

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“…Early research in FPGA placement in both industry and academia often relied on heuristic algorithms based on simulated annealing [6,7], with a notable example being the Versatile Place and Route (VPR) tool [6,8]. These approaches generated initial solutions in a random manner and perturbed the current solution through global or local exchanges, substitutions, movements, duplications, and other operations to generate new solutions, while these methods can yield relatively desirable placement results, they are associated with longer execution times when dealing with large-scale circuit placement problems [9]. In the subsequent development, both industry and academia transitioned towards minimum-cut algorithms for placement research, with a prominent example being PPFF [10].…”

Section: Introductionmentioning

confidence: 99%

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

Liu,

Wang,

2023

Electronics

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Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chips and the escalating scale of system designs, the significance of their accompanying Electronic Design Automation (EDA) tools has never been more pronounced. The placement process, serving as the linchpin in FPGA EDA, directly influences FPGA development and operational efficiency. This paper introduces an FPGA placement methodology hinging on the Verilog-to-Routing (VTR) framework. We introduce a novel packing approach grounded in the weighted Edmonds’ Blossom algorithm, ensuring that the CLB generation strategy aligns more closely with load-balanced distribution. Furthermore, we enhanced the electric field-driven resolver placement process for CLB locations and leverage GPU-accelerated design. Experimental results demonstrate substantial improvements over the traditional VTR algorithm, with an average optimization of 28.42% in the packing process runtime, an average acceleration ratio of 2.85 times in the placement phase, and a 39.97% reduction in total packing and placement runtime consumption.

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Section: Introductionmentioning

confidence: 99%

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

Liu,

Wang,

2023

Electronics

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AiMap+: Guiding Technology Mapping for ASICs via Learning Delay Prediction

Liu,

Zhao

2024

Electronics

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Technology mapping is an essential process in the Electronic Design Automation (EDA) flow which aims to find an optimal implementation of a logic network from a technology library. In application-specific integrated circuit (ASIC) designs, the non-linear delay behaviors of cells in the library essentially guide the search direction of technology mappers. Existing methods for cell delay estimation, however, rely on approximate simplifications that significantly compromise accuracy, thereby limiting the achievement of better Quality-of-Result (QoR). To address this challenge, we propose formulating cell delay estimation as a regression learning task by incorporating multiple perspective features, such as the structure of logic networks and non-linear cell delays, to guide the mapper search. We design a learning model that incorporates a customized attention mechanism to be aware of the pin delay and jointly learns the hierarchy between the logic network and library through a Neural Tensor Network, with the help of proposed parameterizable strategies to generate learning labels. Experimental results show that (i) our proposed method noticeably improves area by 9.3% and delay by 1.5%, and (ii) improves area by 12.0% for delay-oriented mapping, compared with the well-known mapper.

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Timing-Driven Simulated Annealing for FPGA Placement in Neural Network Realization

Cited by 2 publications

References 19 publications

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

AiMap+: Guiding Technology Mapping for ASICs via Learning Delay Prediction

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