2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2020
DOI: 10.1109/async49171.2020.00008
|View full text |Cite
|
Sign up to set email alerts
|

Timing Errors in STA-based Gate-Level Simulation

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2023
2023
2023
2023

Publication Types

Select...
1

Relationship

0
1

Authors

Journals

citations
Cited by 1 publication
(1 citation statement)
references
References 4 publications
0
1
0
Order By: Relevance
“…Gate-level circuit partitioning is a very important phase during EDA simulation [ 1 ]. It divides large-scale circuits into similar-sized subsets, with a minimum number of connections between subsets.…”
Section: Introductionmentioning
confidence: 99%
“…Gate-level circuit partitioning is a very important phase during EDA simulation [ 1 ]. It divides large-scale circuits into similar-sized subsets, with a minimum number of connections between subsets.…”
Section: Introductionmentioning
confidence: 99%