Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits

Abstract

The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit and induces timing constraints that must be properly handled by synthesis tools. This thesis focuses on techniques for timing closure of cellbased VLSI circuits, i.e. techniques able to iteratively reduce the number of timing violations until the synthesis of the synchronous digital system reaches the specified target frequency.