Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Abstract

This paper proposes a discrete multi-tone timing-recovery system with adaptive equalization for ultra-high-speed wireline applications. It combines frequency-domain clock recovery with decisiondirected equalization to improve receiver performance while eliminating the need for pilot carriers, thereby increasing spectral efficiency. Compared to a conventional pilot-carrier-based technique employing four pilot carriers and a 32-point FFT, this approach improves phase-error sensitivity by 3.6 times, tracking bandwidth by 1.7 times, increases the jitter tolerance slope by 20dB per decade at low frequency, and removes residual equalization error, resulting in an overall data-rate increase of 27%. The concept is validated at the system-level and gate-level through synthesis in an FPGA. A convergence analysis of both the adaptive equalizer and clock synchronization shows the system's ability to mitigate error propagation and remain synchronized in the presence of impairments. Finally, we highlight the system's ability to trade-off clock convergence versus phase error sensitivity. Either parameter can be adjusted by 15 times, optimizing the receiver over a broad range of signal conditions.INDEX TERMS Adaptive equalization, clock and data recovery (CDR), decision-directed equalization, discrete multi-tone (DMT), orthogonal frequency division multiplexing (OFDM), SERDES, single-tap equalization, timing recovery, wireline. JEREMY COSSON-MARTIN (Graduate Student Member, IEEE) received the B.A.Sc. degree in electrical engineering from Queen's University, Kingston, ON, Canada, in the spring of 2018. In the fall of 2018, he began an M.A.Sc. program at the University of Toronto, ON, Canada, under the supervision of Prof. A. Sheikholeslami. In 2019, he transferred into a Ph.D. program.In the summer of 2018, he joined Huawei Canada, Toronto, ON, Canada, as an intern, where he was involved in creating in-lab measurement scripts for a prototype 56-Gb/s SerDes integrated chip. He also received experience in 7-nm FinFET layout. Currently, he is researching multi-tone schemes for ultra-high-speed wireline applications.

An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline Applications

“…Although DMT is the most straightforward implementation of multi-carrier signalling, it suffers from two shortcomings. First, the CP adds an overhead that is most pronounced with short frame lengths in bin-limited systems [8] [19]. And second, as shown in Fig.…”

“…Channel estimation is the process of determining the required C[k] to correct linear distortion. Timing recovery deals with finding the ADC sampling frequency and phase that correctly positions the FFT window (coarse synchronization) and minimizes jitter (fine tracking) [19] [26]. Although the channel is assumed short-term stationary, impairments such as jitter and noise cause the overall link response to change continuously.…”

“…A popular approach is to send channel estimation and timing recovery information by transmitting known symbols called pilot carriers. These can either be sent as a periodic training sequence once every few hundred frames, or by reserving a fraction of the bins to send them continuously [19][27] [28][29] [30]. However, the former approach is blind most of the time and results in poor tracking performance [31], whereas the latter gathers information continuously but introduces overhead, particularly for bin-limited systems [30].…”

“…As an example, if we assume a 32-point DMT system and restrict pilot carriers to once every 256 frames, the overhead is negligible; however, from simulation, the tracking bandwidth is reduced by 18 times and no-longer meets the CEI-56G-LR-PAM4 requirement [32]. On the other hand, by reserving four bins to send them continuously, the standard is met, but a 27% overhead is introduced [19]. When including the overhead from three CP, the total overhead worsens to 33%.…”

Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications

“…System-level modeling of a DMT serial link for > 100 Gb/s applications is provided in [22], and [23] compared DMT link and PAM-2/4/8 for ultra-high-speed links both with smooth channels and multi-drop-bus (MDB) interfaces. Timing recovery system with adaptive equalization for wireline DMT links is proposed in [24].…”