Timing Verification for Adaptive Integrated Circuits

Abstract

An adaptive circuit can perform built-in self-detection of timing variations and accordingly adjust itself to avoid timing violations. Compared with conventional over-design approach, adaptive circuit design is conceptually advantageous in terms of power-efficiency. Although the advantage has been witnessed in numerous previous works including test chips, adaptive design is far from being widely used in practice.A key reason is the lack of corresponding timing verification support. We developed new timing analysis techniques to fill this void. A main challenge is the large runtime complexity due to numerous adaptivity configurations. We propose several pruning and reduction techniques and apply them in conjunction with statistical static timing analysis (SSTA). The proposed method is validated on benchmark circuits including the recent ISPD'13 suite, which has circuit as large as 150K gates. The results show that our method can achieve orders of magnitude speed-up over Monte Carlo simulation with about the same accuracy. It is also several times faster than an exhaustive application of SSTA.

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era

“…To counter the aging effects actively, postsilicon tuning techniques can also be applied to adjust the timing properties of individual chips. Techniques in this category include body bias tuning [66], [67], voltage control [68], [69], [70] as well as clock tuning [71], [72], [73].…”

Proximity Optimization for Adaptive Circuit Design

“…Moreover, the placement is legal and routable everywhere, which means later when incremental placement is performed in stage 2, no effort will be made in eliminating overlap. The statistical STA tool we applied [3] derived from the timer introduced in [1].…”

“…The statistical timing computation is then performed with a PERT (Program Evaluation and Review Technique) -like circuit graph traversal [1]. As tested on ISCAS'85 circuits, errors of the statistical STA results compare to Monte Carlo simulation results on mean (µ) and standard deviation (σ) are 0.04% and 5.7% respectively [3], which are acceptable for our application.…”

“…The timing yield of adaptive designs is estimated by the technique of [3]. All the implementations run on an AMD Opteron processor with 2.2GHz frequency, 4GB memory and Linux operating system.…”

“…3: Experimental results with only forward body bias (FBB). Total area overhead, power overhead, and wire-length increase are denoted by ∆A, ∆P wr, and ∆W ire, respectively.Table 3.4: Experimental results with Adaptive Body bias (ABB).…”