Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores

Abstract

In the Internet-Of-Things (IoT) domain, microcontrollers (MCUs) are used to collect and process data coming from sensors and transmit them to the cloud. Applications that require the range and precision of floating-point (FP) arithmetic can be implemented using efficient hardware floating-point units (FPUs) or by using software emulation. FPUs optimize performance and code size, whilst software emulation minimizes the hardware cost. We present a new area-optimized, IEEE 754-compliant RISC-V FPU (Tiny-FPU), and we explore the area, code size, performance, power, and energy efficiency of three different implementations of the RISC-V Instruction Set Architecture double and singleprecision FP extensions on an MCU-class processor. We show that Tiny-FPU, in its double and single-precision versions, is respectively 54% and 37% smaller than a double and singleprecision FPU optimized for performance and energy efficiency. When coupling a RISC-V core with Tiny-FPU, we achieve up to 18.5× and 15.5× speedups with respect to the same core emulating FP operations via software.

Design and implementation of RISC-V-based vector operation unit for embedded processor

“…RISC-V is a new Instruction Set Architecture [5] (ISA), completely open source, originally developed by researchers at the University of California, Berkeley. The architecture is suitable for implementation in hardware and is not only suitable for analog or binary translation, but also supports user-level ISA extensions [6][7][8][9][10][11][12][13] .…”

RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors

“…Researchers have proposed different solutions to provide FP capabilities to a core when the system area is strictly constrained. When a full-fledged FPU leads to an excessive area increase, designers can integrate a slower but tiny FPU, crafted for tightly constrained IoT cores [2]. Another possibility is to implement hardware/software approaches, in which hardware optimizations in the integer datapath speed up critical operations used in the FP emulation libraries [13].…”

A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor

“…As a bridge to undertake hardware kernel design and algorithm library design, ISA also needs a faster decision-making method. In this work, We focus on the fixed-point RISC-V instruction architecture, ensur-IEICE Electronics Express, Vol.VV, No.NN, 1-6 ing low design cost without the floating-point unit (FPU) [20,24,25,28,29,30,31]. In this way, such a design can improve hardware reusability.…”