Tiny Tera: a packet switch core

McKeown, Nick; Izzard, Martin; Mekkittikul, A.; Ellersick, William F.; Horowitz, Mark

doi:10.1109/40.566194

Cited by 242 publications

(108 citation statements)

References 12 publications

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“…Most implementation proposals for WFQ utilize the centralized nature of the operation of a switch and assume fixedsize packets to provide fair queuing [1], [14]. In typical WFQ implementations on centralized routers, a WFQ algorithm at each egress port executes independently and in parallel with those at other egress ports [15].…”

Section: B Wfq Implementationsmentioning

confidence: 99%

Implementation of WFQ in a distributed open software router

Khan

Sahoo

Manjunath

2011

2011 IEEE 36th Conference on Local Computer Networks

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WFQ is a widely used scheduler that enables QoS features in a router. The inherent centralized nature of the design of WFQ schedulers in most switches and routers creates several challenges when exported to distributed architectures. In this paper, we study the challenges of implementing WFQ in a distributed OSR, propose some novel techniques to address these challenges and compare the performance of our WFQ implementation in distributed OSR with that of a centralized WFQ scheme.

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Section: B Wfq Implementationsmentioning

confidence: 99%

Implementation of WFQ in a distributed open software router

Khan

Sahoo

Manjunath

2011

2011 IEEE 36th Conference on Local Computer Networks

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“…The fabric of a crossbar-based packet switch can be either unbuffered [1] or internally buffered [2]. The similarity between these two variants lies in the quadratic growth of their cost with the number of switch ports.…”

Section: Introductionmentioning

confidence: 99%

“…The crossbar-based fabric switch is the dominant architecture for today's high-performance packet switches [1] [2]. The fabric of a crossbar-based packet switch can be either unbuffered [1] or internally buffered [2].…”

Section: Introductionmentioning

confidence: 99%

Buffered Crossbar Fabrics Based on Networks on Chip

Mhamdi

Goossens

Senin

2010

2010 8th Annual Communication Networks and Services Research Conference

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Abstract-Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratically with the port count. Additionally, similar to traditional crossbars, point-to-point switching mandates the use of long wires to connect inputs to outputs, resulting in non-negligible delays. In this paper, we propose a CICQ switching architecture where the buffered crossbar fabric is designed using a Network on Chip (NoC). Instead of a dedicated buffer for every pair of input-output ports, we use on-chip routers, one for each crosspoint. Our design offers several advantages when compared to traditional CICQs: 1) speedup, because the fabric can operate faster due to the small size of the NoC routers, their distributed arbitration and the short wires connecting them. This is in contrast to single-hop crossbars that use long wires and centralized arbitration. 2) Load balancing, because flows from different input-output port pairs share the same router buffers, contrary to the internal buffers of traditional CICQs that are dedicated to a single input-output pair. 3) Path diversity, allowing traffic from an input port to follow different paths to its destination output port. This results in further load balancing, especially for non-uniform traffic, and provides better fault tolerance in the presence of interconnect failures. We analyzed the performance of our architecture by simulation and presented its performance under wide traffic conditions and switch sizes. We prototyped, in CMOS technology, a 32×32 NoC-based crossbar switch. The implementation results suggest that we can clock the switch at a frequency of 413 MHZ, reaching an aggregate throughput in excess of 10 10 ATM cells per second.

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“…iSLIP is a good example of an iterative matching scheme. Although iSLIP provides 100% throughput for uniform independent traffic, because of the arbitration time and connection state amount of this arbitration scheme, it has been proposed for a small number of ports [7] due to its centralized implementation (i.e., 32 for iSLIP). Transmission of phases: request, grant, and acknowledge are performed within a cell slot between input and output arbiters.…”

Section: Introductionmentioning

confidence: 99%

CIXB-1: combined input-one-cell-crosspoint buffered switch

Rojas‐Cessa¹,

Oki

Jing

et al.

2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)

174

159

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Buffered crossbars have been considered as an alternative for non-buffered crossbars to improve switching throughput. The drawback of a buffered crossbar is the memory amount that is proportional to the square of the number of ports (O N 2 ). This is not the main limitation when the buffer size is kept to a minimum size such that implementation is feasible. For a small buffer size, the number of ports of a switch module is not limited by the memory amount but by the pin count. We propose a novel architecture: a Combined Input-One-cell-Crosspoint Buffer crossbar (CIXB-1) with Virtual Output Queues (VOQs) at the inputs and round-robin arbitration. We show that the proposed architecture can provide 100% throughput under uniform traffic. A CIXB-1 offers several advantages for a feasible implementation such as scalability and timing relaxation. With the currently available memory technology, a one-cell crosspoint buffered switch is feasible for a 32 32 fabric module.

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Tiny Tera: a packet switch core

Cited by 242 publications

References 12 publications

Implementation of WFQ in a distributed open software router

Implementation of WFQ in a distributed open software router

Buffered Crossbar Fabrics Based on Networks on Chip

CIXB-1: combined input-one-cell-crosspoint buffered switch

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