Tolerance of performance degrading faults for effective yield improvement

Hsieh, Tong-Yu; Breuer, M.A.; Annavaram, Murali; Gupta, Sandeep; Lee, Kuen-Jong

doi:10.1109/test.2009.5355594

Cited by 24 publications

(7 citation statements)

References 8 publications

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“…However, the proposed method does not achieve full coverage of stuck-at faults, and requires very long test times. In [7], the authors use faults in BPUs as the typical example of the so-called Performance Degrading Faults, and analyze their impact on the performance of a processor, showing that their proper identification can significantly help to improve the yield.…”

Section: Introductionmentioning

confidence: 99%

On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture

Sanchez¹,

Reorda²,

Tonda³

2012

VLSI-SoC: Advanced Research for Systems on Chip

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Abstract. Branch Prediction Units (BPUs) are commonly used in pipelined processors, since they can significantly decrease the negative impact of branches in superscalar and RISC architectures. Traditional solutions, mainly based on scan, are often inadequate to effectively test these modules: in particular, scan does not represent a viable solution when Incoming Inspection or on-line test are considered. Functional test may stand as an effective solution in these situations, but requires effective algorithms to be available. In this paper we propose a functional approach targeting the test of BPUs based on the Branch History Table (BHT) architecture; the proposed approach is independent on the specific implementation of the BPU, and is thus widely applicable. Its effectiveness has been validated on a BPU resorting to an opensource computer architecture simulator and to an ad hoc developed HDL testbench. Experimental results show that the proposed method is able to thoroughly test the BPU, reaching complete static fault coverage with reasonable requirements in terms of test program size and execution time.

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Section: Introductionmentioning

confidence: 99%

On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture

Sanchez¹,

Reorda²,

Tonda³

2012

VLSI-SoC: Advanced Research for Systems on Chip

View full text Add to dashboard Cite

show abstract

“…However, the proposed method does not achieve full coverage of stuck-at faults, and requires very long test times. In [6], the authors use faults in BPUs as the typical example of the so-called Performance Degrading Faults, and analyze their impact on the performance of a processor, showing that their proper identification can significantly help improving the yield.…”

Section: Introductionmentioning

confidence: 99%

On the functional test of Branch Prediction Units based on Branch History Table

Sánchez

Reorda

Tonda

2011

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip

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Branch Prediction Units (BPUs) are highly efficient modules that can significantly decrease the negative impact of branches in superscalar and RISC processors. Traditional test solutions, mainly based on scan test, are often inadequate to tackle the complexity of these architectures, especially when dealing with delay faults that require at-speed stimuli application. Moreover, scan test does not represent a viable solution when Incoming Inspection or on-line test are considered. In this paper a functional approach targeting BPU test is proposed, allowing to generate a suitable test program whose effectiveness is independent on the specific implementation of the BPU. The effectiveness of the approach is validated on a Branch History Table (BHT) resorting to an open-source computer architecture simulator and to an ad hoc developed HDL testbench. Experimental results show that the proposed method is able to thoroughly test the BHT, reaching complete static fault coverage.

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“…For instance, many have exploited microarchitecture property of caches to tolerate defects [3] [4] [5] [6]. The fact that branch predictors are speculative has also been studied for the purpose of DT in [7]. However, there is no systematic methodology to guide the development of such advanced approaches and there is no study on using implicit redundancy for datapath modules.…”

mentioning

confidence: 99%

A multi-layered methodology for defect-tolerance of datapath modules in processors

Hsiung

Gupta

2015

2015 IEEE 33rd VLSI Test Symposium (VTS)

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Technology scaling increases circuits' susceptibility to manufacturing imperfections and dramatically decreases processor yields. Traditional defect-tolerance approaches add explicit redundant circuitry to improve yield and hence are very expensive for datapath modules in processors. We propose a multi-layered methodology to develop new and efficient defect-tolerance approaches for processors. Specifically, we develop a microarchitecture layer approach for arithmetic logic units (ALU), a circuit layer approach for multipliers, and an ISA layer approach for floating-point units (FPU). We demonstrate that our three approaches improve performance-per-fabricated-die-area of a modern processor core by 3.5%, 2.4%, and at least 9%, and hence collectively provide significant gains. INTRODUCTIONTechnology scaling has increased transistor density and reduced fabrication cost per transistor. To efficiently utilize these, processor designers pack more functionality and more performance enhancing features into each new processor. However, as technology advances deep into nano-scale, the improvements in cost, power, and delay, provided by each technology generation have started to slow down, or even reverse. One reason is increase in circuits' susceptibility to manufacturing imperfections. We use the term defect to refer to two types of imperfections, namely, process variations and random defects that affect circuit operation. Defect rates are now increasing with each scaling generation and hence reducing yield, especially at the top-levels of performance. Reduction in yield diminishes or may even negate reduction in die fabrication cost provided by scaling.Traditionally, use of explicit redundancy has been explored in memory and logic circuits to improve yield. Spare rows and columns are commonly used in memories [1] [2]. However, cost of such explicit circuit redundancy is prohibitively high for logic circuits, such as most datapath modules. Recent advanced defecttolerance (DT) approaches for processors use implicit redundancy, i.e., utilize existing features in processors and add a minimal level of reconfiguration to achieve DT with low overheads. For instance, many have exploited microarchitecture property of caches to tolerate defects [3] [4] [5] [6]. The fact that branch predictors are speculative has also been studied for the purpose of DT in [7]. However, there is no systematic methodology to guide the development of such advanced approaches and there is no study on using implicit redundancy for datapath modules.In this work, we propose a methodology to develop implicitredundancy DT approaches for processors. The methodology systematically develops approaches to maximize fabrication efficiency, which is measured as performance-per-fabricateddie-area (or performance-per-area). In particular, we propose new and efficient approaches for datapath modules used in processors, namely, ALU, fixed-point multiplier, and FPU. In this work, we use a single core processor to demonstrate that our three approaches collectively provid...

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Tolerance of performance degrading faults for effective yield improvement

Cited by 24 publications

References 8 publications

On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture

On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture

On the functional test of Branch Prediction Units based on Branch History Table

A multi-layered methodology for defect-tolerance of datapath modules in processors

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