Tool Support for Consistency Verification of UML Diagrams

Phuklang, Salilthip; Yokogawa, Tomoyuki; Leelaprute, Pattara; Arimoto, Kazutami

doi:10.1007/978-3-319-69926-4_51

Cited by 2 publications

(2 citation statements)

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“…We adopt a similar verification framework to [16] for a sequence diagram and state machine diagrams. Fig.…”

Section: Framework Of Consistency Verificationmentioning

confidence: 99%

“…Yokogawa et al [14] developed a method for inter-model consistency verification of a sequence diagram and state machine diagrams using the FDR model checker [15]. Phuklang et al [16] developed a tool supporting to conduct consistency verification. Those studies can successfully detect several types of inconsistencies between state machine diagrams and a sequence diagram.…”

Section: Introductionmentioning

confidence: 99%

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Synthesis and Consistency Verification of UML Sequence Diagrams with Hierarchical Structure

Matsumoto

Yokogawa

Amasaki

et al. 2020

Information Engineering Express

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Automatic consistency checking for UML state machine diagrams and sequence diagrams has been expected since developers spend considerable effort to keep the consistency. In particular, the verification of diagrams with a hierarchical structure is required. Although formalization of state machine diagrams with hierarchical structure has been widely treated, it is not yet sufficient for sequence diagrams. In this paper, we propose an automatic method for verifying the consistency between state machine diagrams and sequence diagrams with a hierarchical structure. In our verification framework, the consistency of diagrams is defined as an inclusive relation between the sets of traces and is checked using the FDR model checker. FDR can check refinement relation between processes described as CSP M notation. We provide a process description of state machine diagrams and sequence diagrams and can verify the consistency by checking traces inclusion of processes using FDR. Our description supports for sequence diagrams with a hierarchical structure. We applied the proposed process representation to an example diagram that describes interactions of basic components of a wireless sensor network system and showed that the hierarchical behavior of the diagram could be correctly represented.

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“…We adopt a similar verification framework to [16] for a sequence diagram and state machine diagrams. Fig.…”

Section: Framework Of Consistency Verificationmentioning

confidence: 99%