Top-Down Fabricated Reconfigurable FET With Two Symmetric and High-Current On-States

Abstract

We demonstrate a top-down fabricated reconfigurable field effect transistor (RFET) based on a silicon nanowire that can be electrostatically programmed to pand n-configuration. The device unites a high symmetry of transfer characteristics, high on/off current ratios in both configurations and superior current densities in comparison to other top-down fabricated RFETs. Two NiSi2/Si Schottky junctions are formed inside the wire and gated individually. The narrow omega-gated channel is fabricated by a repeated SiO2 etch and growth sequence and a conformal TiN deposition. The gate and Schottky contact metal work functions and the oxide-induced compressive stress to the Schottky junction are adjusted to result in only factor 1.6 higher p-than n-current for in absolute terms identical gate voltages and identical drain voltages.

A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors

“…[31] Further, the gate and Schottky contact metal work functions and the oxide-induced compressive stress to the Schottky junction could be adjusted to lift the asymmetry of the injection barriers for holes and electrons. [13] Importantly, the possibility of changing the configuration of each transistor within a circuit enables a reconfiguration of its specific logic functions during operation. [32] Further, the bidirectional nature of reconfigurable transistors is a clear advantage for flexible and adaptive circuit design, as equivalent results can be obtained by swapping the signals between source/drain and V PG /V CG .…”

“…With the use of Si channels and Ni x Si 1-x contacts various concepts with two or more independent gates have been proven experimentally. [8][9][10][11] Remarkably, symmetry in the output characteristics of p-and n-operation has been reached by the use of strain engineering both on bottom-up [12] and top-down Si nanowire RFETs [13] . Despite those outstanding efforts it has been noted, that the enhancement of the drive current and the reduction of dynamic power consumption strongly scales with the reduction of the respective Schottky barrier heights for electrons and holes.…”

On the Operation Modes of Dual-Gate Reconfigurable Nanowire Transistors

“…This is particularly detrimental to the PGAS mode, leading to a complete loss of noise margin. However, concerning the PGAD mode, it has been shown that highly scaled devices with a short screening length λ (representing the characteristic length on which potential variations are being screened [19], [20]) can also exhibit a linear output characteristic at room temperature due to the strongly increased tunneling probability through the Schottky barrier [8], [21].…”

“…Recently, reconfigurable field-effect transistors (RFETs) have attracted increasing attention because they utilize electrostatic doping to create virtual n-/p-regions avoiding dopant-related issues. Moreover, they can be tuned to operate as n-/p-transistors with unipolar device operation similar to conventional MOSFETs [4]- [8]. Previous work using trigates [4], [5], i.e., two gates for creating virtual source/drain regions and the third one for ON/OFF switching, has demonstrated reconfigurable devices with high I ON /I OFF ratio and steep switching behavior.…”

“…The adoption of three gates will certainly need more space and might become a key limiting factor for downscaling. Hence, devices using only a dual-gate architecture have been investigated [6]- [8] and the impact of process fluctuations in device fabrication has been studied [9]. In these devices, typically, the gate at the drain side is used to 'program' the device either to n-or p-type configuration, while the gate at the source side is used as the switching or control gate.…”