Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Abstract

This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p -channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage ( V th ) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al 2 O 3 ) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V th shift (Δ V th ) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.

Investigation of Electrical Behaviors Observed in Vertical GaN Nanowire Transistors Using Extended Landauer-Büttiker Formula

“…By optimizing gate dielectric material, gate hysteresis can be reduced during voltage sweep resulting in almost-zero threshold voltage shift (ΔVth). To ease the discussion from the results obtained in this study, from this point forward, the devices fabricated by Yu et al [9] and Fatahilah et al [11] are assigned as GaN-FETSiO2 and GaN-FETAl2O3, respectively. Moreover, those two vertical GaN NW FETs embedded different doped materials for their channels (i.e., unintentionally doped i-GaN and p-GaN, respectively), in which their original layer stacks were grown by metalorganic vapour-phase epitaxy (MOVPE) [9], [11].…”

“…We study the nonlinear behavior of drain current from two different types of vertical GaN nanowire transistors fabricated by Yu et al [9] and Fatahilah et al [11]. The striking difference between those two devices is their gate dielectric materials.…”

“…After the GaN NWs have been prepared, a 20-nm-thick SiO2 as a dielectric layer was deposited on their a-plane sidewalls at 300 o C by plasma-enhanced atomic layer deposition (PEALD), using triethoxysilane and oxygen plasma as the silicon and oxygen precursors, respectively. However, it should be noted that to minimize gate hysteresis during forward and backward sweeps, ~25 nm thick Al2O3 could be opted instead of SiO2 as gate dielectric layer [11]. Then, a 200-nm-thick SiOx as a passivation layer between highly doped source layer and gate metal was deposited by e-beam evaporation.…”

“…Several device design and processing optimizations were conducted (e.g., introduction of the p-type channel, insertion of mesa mechanical support, and change of gate oxide from SiO2 to Al2O3 thin films), allowing higher threshold voltages, enhanced joining technique of the device with characterization instruments, and reduction of gate hysteresis to nearly zero level under different current sweep directions, respectively [11]- [13]. Moreover, they have demonstrated current upscaling capability of the devices by realizing and measuring transistors with different numbers of integrated GaN nanowires on a single 2-inch wafer.…”

“…The model was developed by extending the "ideal wire" of Landauer-Büttiker's work with an almost one-dimensional case, where the resulting current is directly proportional to the density of states (DOS) and the quasi-Fermi level, implying that the conductance is also directly proportional to the DOS [27]. To check the accuracy of the model, the theoretical results were compared to the experimental data in Yu et al [9] and Fatahillah et al [11] using three fitting parameters. By using a simple formulation, we also discuss gating hysteresis in the device, which is mediated by the selected oxide layer interface.…”