TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers

Abad, Pablo; Prieto, Pablo; Menezo, Lucía G.; Colaso, Adri ́n; Puente, Valentín; Gregorio, J.A.

doi:10.1109/nocs.2012.19

Cited by 61 publications

(23 citation statements)

References 24 publications

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“…The error produced by the real-time simulation was not larger than 5.8 % (for time = 26 min), while the error produced by discrete mode was not higher than 6.2 % (for time = 59 min). These errors are acceptable according to similar results presented in [29][30][31] for experiments of an equivalent nature. Considering that we configured our simulator to not consider the TCP/IP processing cost, based on the capabilities of the TCP Offload Engine (TOE [32]) network interfaces, we attributed these differences to the execution of some TPC/IP operations on the processor, since, unfortunately, the TOE technology available on the computers used in this experiment does not support the full layer set of the TPC/IP protocol.…”

Section: Validation Of the Performance Datasupporting

confidence: 85%

A novel caching algorithm for VoD proxy implementation and its evaluation including a new set of metrics for efficiency analysis

2015

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Background: Video on demand (VoD) is a fast-growing digital service that requires a substantial amount of hardware resources for its implementation. To reduce the costs of running this service, an alternative is to use proxies that cache the most important portions of the video collection in order to meet the demand for this content in place of the primary server of the VoD system. Methods: To improve the efficiency of the proxies, we proposed a novel caching algorithm that explores the positioning of the active clients to determine the density of clients inside a time window existing in front of each video chunk. The algorithm attributes a higher caching priority to the video chunks with greater aggregate density in the memory. To evaluate our approach, we compared it with others of similar nature using both traditional metrics like hit ratio, as well as physical metrics such as the use of processing resources. This complementary set of metrics is produced by our simulator that, as far as we know, is the first one of its kind to enable the evaluation of hardware consumption used to implement the VoD proxy. Results: Results show that the novel algorithm can achieve a higher hit ratio while requiring a little more effort from the hardware. Additionally, it was identified that the processor constitutes the major bottleneck to this application when demand increases. Conclusions: Among the recent emergence of caching strategies which consider the positioning of clients as criterion for caching, the strategy of prioritizing the chunks with greater density of previous clients showed to be a more efficient solution.

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Section: Validation Of the Performance Datasupporting

confidence: 85%

A novel caching algorithm for VoD proxy implementation and its evaluation including a new set of metrics for efficiency analysis

2015

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“…A wide variety of software on-chip network simulators are publicly available, each with a different set of features and strengths [2,3,11,21,33]. In addition, many multiprocessor simulators include an on-chip network, or support integration with a dedicated on-chip network simulator [8,20,30].…”

Section: Related Workmentioning

confidence: 99%

“…There is a number of software simulators publicly available that are in wide use today [2,3,11,21,33]. However, while software models are faster to develop, they face scalability challenges.…”

mentioning

confidence: 99%

OpenSoC Fabric

Fatollahi-Fard

Donofrio

Shalf

2014

Proceedings of the 2014 International Workshop on Network on Chip Architectures

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Recent advancements in technology scaling have sparked a trend towards greater integration with large-scale chips containing thousands of processors connected to memories and other I/O devices using non-trivial network topologies. Software simulation suffers from long execution times or reduced accuracy in such complex systems, whereas hardware RTL development is too time-consuming. We present OpenSoC Fabric, a parameterizable and powerful on-chip network generator for evaluating future large-scape chip multiprocessors and SoCs. OpenSoC Fabric leverages a new hardware DSL, Chisel, which contains powerful abstractions provided by its base language, Scala, and generates both software (C++) and hardware (Verilog) models from a single code base. This is in contrast to other tools readily available which typically provide either software or hardware models, but not both. The OpenSoC Fabric infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, is open-source, and uses object-oriented design and functional programming to make functionality extension as easy as possible.

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“…It can interface with RSIM [28] and SimOS [33] to perform fullsystem simulation. Topaz [1] is a recently released extension of SICOSYS capable of interfacing with Gems to perform full-system simulation of CMPs. The Gem5 simulator [12], which merges the well-known M5 [11] and Gems simulators, has support for most state-of-the-art processor technologies while providing flexible models for the memory subsystem.…”

Section: Simulation Of Future Many-core Systemmentioning

confidence: 99%

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation

Navaridas

Khan

et al. 2012

2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip

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Abstract-Architectural simulation is an essential tool when it comes to evaluating the design of future many-core chips. However, reproducing all the components of such complex systems precisely would require unreasonable amounts of computing power. Hence, a trade off between accuracy and compute time is needed. For this reason most state-of-the-art tools do not have accurate models for the networks-on-chip, and rely on timing models that permit fast-simulation. Generally, these models are very simplistic and disregard contention for the use of network resources. As the number of nodes in the network-on-chip grows, fluctuations with contention and other parameters can considerably affect the accuracy of such models. In this paper we present and evaluate a collection of timing models based on a reservation scheme which consider the contention for the use of network resources. These models provide results quickly while being more accurate than simple no-contention approaches.

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TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers

Cited by 61 publications

References 24 publications

A novel caching algorithm for VoD proxy implementation and its evaluation including a new set of metrics for efficiency analysis

A novel caching algorithm for VoD proxy implementation and its evaluation including a new set of metrics for efficiency analysis

OpenSoC Fabric

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation

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