Topological-Graph Dependencies and Scaling Properties of a Heuristic Qubit-Assignment Algorithm

Abstract

The qubit-mapping problem aims to assign and route qubits of a quantum circuit onto a NISQ device in an optimized fashion, with respect to some cost function. Finding an optimal solution to this problem is known to scale exponentially in computational complexity; as such, it is imperative to investigate scalable qubit-mapping solutions for NISQ computation. In this work, a noise-aware heuristic qubit-assignment algorithm (which assigns initial placements for qubits in a quantum algorithm to qubits on a NISQ device, but does not route qubits during the quantum algorithm's execution) is presented and compared against the optimal brute-force solution, as well as a trivial qubit assignment, with the aim to quantify the performance of our heuristic qubit-assignment algorithm. We find that for small, connectedgraph algorithms, our heuristic-assignment algorithm faithfully lies in between the effective upper and lower bounds given by the brute-force and trivial qubit-assignment algorithms. Additionally, we find that the topological-graph properties of quantum algorithms with over six qubits play an important role in our heuristic qubit-assignment algorithm's performance on NISQ devices. Finally, we investigate the scaling properties of our heuristic algorithm for quantum processors with up to 100 qubits; here, the algorithm was found to be scalable for quantum-algorithms which admit path-like graphs. Our findings show that as the size of the quantum processor in our simulation grows, so do the benefits from utilizing the heuristic qubitassignment algorithm, under particular constraints for our heuristic algorithm. This work thus characterizes the performance of a heuristic qubit-assignment algorithm with respect to the topological-graph and scaling properties of a quantum algorithm which one may wish to run on a given NISQ device.

Low-Depth Flag-Style Syndrome Extraction for Small Quantum Error-Correction Codes

“…Our work also shows that much optimization is left at the level of quantum compilation before running stabilizer circuits on hardware; indeed, several studies have shown that topological-graph properties associated with circuit-level qubit interactions play an important role in suppressing errors for NISQ-era algorithms [32]- [35], and error-correction algorithms are no exception. It would be interesting to evaluate whether such lower-depth syndrome-extraction sequences as ours would be amenable still to NISQ-era devices, given their restricted connectivity, and whether or not current strategies such as parallel syndrome extraction [10] could be utilized for further gate reductions.…”

Quantum Machine Learning Techniques Integrated in Quantum Software Testing

“…The maintenance phase includes changes, modifications, and updates to the customer-related QSE. QC is a trending area for research in QSE, focusing mainly on classical software systems integrated with quantum algorithms [23]. Quantum Computers are more cost-effective to design because they adopt existing classical software systems.…”

Mapping Quantum Circuits to Modular Architectures with QUBO

“…However, solving the quantum circuit mapping problem for a large number of qubits can be computationally unfeasible, even for contemporary single-core devices. To tackle it, diverse mapping algorithms have been proposed, including heuristic or brute-force strategies, graph-theoretical techniques, dynamic programming algorithms, and machine learning-based solutions [2,7,10,[17][18][19][20][21][22][23][24].…”

“…In order to improve their initial approach in terms of circuit and graph partitioning with an overly-restricting local lookahead function, we rely on previous subgraph isomorphism- [21,24,[30][31][32] and QUBO optimization-based single-core solutions [33,34] where now instead of mapping logical qubits to optimal subsets of coupling graph representing the physical qubits and their connections (Fig. 1) we map qubits to different cores.…”