Topological routing to maximize routability for package substrate

Liu, Shenghua; Chen, Guoqiang; Jing, Tom Tong; He, Lei; Zhang, Tianpei; Dutta, Robi; Hong, Xianlong

doi:10.1145/1391469.1391612

Cited by 6 publications

(44 citation statements)

References 7 publications

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“…We use the same problem formulation and data structure as [7]. These as well as baseline algorithms for comparison are discussed in this section.…”

Section: Preliminaries and Problem Formulationmentioning

confidence: 99%

“…For example, a very recent substrate routing algorithm displayed a good reported routability in the literature and is used in a state of the art commercial tool. It proposed "dynamic pushing" to tackle the routing order problem and "flexible via staggering" to improve the routability, resulting in 3.5% net unrouted for nine industrial designs [7]. However, the congestion reduction method of iteratively avoiding routing through congested area in [7] limited its advantage in routability.…”

Section: Introductionmentioning

confidence: 99%

“…The window is released after the congestion is eliminated. Compared with the recent substrate routing [7], D-Router reduces the number of unrouted nets by 4.6x, with up to 94x runtime reduction.…”

Section: Introductionmentioning

confidence: 99%

“…Surf assumes a fixed end point, while our formulation in this paper and [7] uses end-zone, though geometrical layout is not considered in both papers.…”

Section: Introductionmentioning

confidence: 99%

“…To better appreciate D-Router, we also implement a negotiation based substrate routing, which obtains similar routability and runtime as [7] and therefore is inferior to D-Router. In addition to negotiation based routing [8,9], a recent onchip router, BoxRouter, also achieves good routability [4], where all nets within a congested window are ripped-up and rerouted simultaneously by an integrity linear programming (ILP) method.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Diffusion-driven congestion reduction for substrate topological routing

Liu

Chen²,

Jing

et al. 2009

Proceedings of the 2009 International Symposium on Physical Design

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Off-chip substrate routing for high density packages is challenging, and the existing substrate routing algorithms often result in a large number of unrouted nets that have to be routed manually. This paper develops an effective yet efficient diffusion-driven method D-Router to improve routability by a simulated diffusion process based on the duality between congestion and concentration. Compared with a recently published A*-based algorithm used in a state of the art commercial tool and with similar routability and runtime as the negotiation based routing, D-Router reduces the number of unrouted nets by 4.6x with up to 94x runtime reduction.

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“…We use the same problem formulation and data structure as [7]. These as well as baseline algorithms for comparison are discussed in this section.…”

Section: Preliminaries and Problem Formulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Surf assumes a fixed end point, while our formulation in this paper and [7] uses end-zone, though geometrical layout is not considered in both papers.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Diffusion-driven congestion reduction for substrate topological routing

Liu

Chen²,

Jing

et al. 2009

Proceedings of the 2009 International Symposium on Physical Design

Self Cite

View full text Add to dashboard Cite

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Implementation of 32nm MD5 Crypto-Processor using Different Topographical Synthesis Techniques and Comparison with 500nm Node

Jimenez

Borja

Silly

et al. 2021

2021 IEEE Fifth Ecuador Technical Chapters Meeting (ETCM)

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This work focuses on several synthetizations developed in both 32nm and 500nm technologies to evaluate the performance differences of MD5 Crypto-Processor. We decided to conduct a topographical synthesis instead of a nontopographical synthesis as it takes more parameters into account to create a more accurate design. We started by comparing some basic cells like inverters and register banks to understand the main differences between the two technologies. Several approaches were considered at this point to understand how different synthetization parameters affect the chip performance and characteristics. These different approaches were focused on time, power and area, and balanced configurations of synthesis flow. Finally, after comparing the performance given by the different approaches in basic digital structures, the balanced approach was implemented in 32nm and benchmarked with the 500nm implementation. Our conclusions were consistent among the various tests conducted and by downscaling we can expect a 10x increase in the clock frequency, a 100x decrease in power consumption, and around a 300x decrease in the area while using the 32nm technology. As a result, we developed a method to fairly compare complex systems to allow a designer to consider if the benefits justify the costs for a technology change.

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ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip

Zheng

Tseng

et al. 2021

2021 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

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To meet the ever-increasing requirements of onchip communication, the trend is towards wavelength-routed optical networks-on-chip (WRONoCs), which support high-speed communication with low power. A typical WRONoC design flow consists of two consecutive steps: topological design and physical design. Current physical design tools interpret the input topology as a pure logic scheme and perform placement and routing for all network components from scratch. Due to the large design complexity and the layout constraints, additional waveguide crossings in the synthesized layouts are hardly avoidable, which results in an increase in insertion loss and crosstalk noise and thus degrades the network performance. In this work, we propose a physical design tool, ToPro, which retains the interconnection among the optical switching elements by projecting the structure of a WRONoC topology onto the physical plane, and focuses on the waveguide routing to the IP-cores. To avoid the increase in insertion loss and crosstalk noise, ToPro removes the extra crossings and long detours of waveguides by changing the routing order of nets. The experimental results demonstrate the superiority of ToPro in time-and energy-efficiency. For example, compared to a state-of-the-art design automation tool, ToPro synthesizes a network with 16 IP-cores with a 17% reduction on the worst-case insertion loss and decreases the synthesis time from more than six days to less than one second.

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Topological routing to maximize routability for package substrate

Cited by 6 publications

References 7 publications

Diffusion-driven congestion reduction for substrate topological routing

Diffusion-driven congestion reduction for substrate topological routing

Implementation of 32nm MD5 Crypto-Processor using Different Topographical Synthesis Techniques and Comparison with 500nm Node

ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip

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