Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

Bhanu, P. Veda; Kulkarni, Pranav Venkatesh; Soumya, J; Cenkarmaddi, Linga Reddy; Idsøe, Henning

doi:10.1109/prime.2018.8430343

Cited by 7 publications

(4 citation statements)

References 14 publications

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“…Though, the Torus topology has many advantages in terms of communication cost, power consumption, and network latency, there are very few approaches that have considered it for the fault-tolerant application-mapping. One of our previous works presented in [23], has targeted Torus topology and performed faulttolerant application-mapping. We have extended the work proposed in [10], [17]- [19] and compared the results in terms of communication cost.…”

Section: Related Workmentioning

confidence: 99%

“…We have extended the work proposed in [10], [17]- [19] and compared the results in terms of communication cost. However, the work addressed in [23] has limited to static simulations. Recently, the authors in [21], [22], [24], [25] have addressed the problem of application mapping onto NoC topologies without considering any core faults in the application.…”

Section: Related Workmentioning

confidence: 99%

“…Most of the researchers have been successful in applying the discrete version of PSO (DPSO) to address the problem of application mapping in NoC. With this motivation, the authors [16], [23] have applied the DPSO to solve the problem of fault-tolerant application mapping onto Mesh and Torus topology, respectively. The detailed description of PSO can be known from [23].…”

Section: B Pso Formulationmentioning

confidence: 99%

“…With this motivation, the authors [16], [23] have applied the DPSO to solve the problem of fault-tolerant application mapping onto Mesh and Torus topology, respectively. The detailed description of PSO can be known from [23]. Since, PSO is one of the contributions in this paper; therefore, authors feel it is necessary to discuss in brief about PSO for the fault-tolerant application mapping onto Torus topology.…”

Section: B Pso Formulationmentioning

confidence: 99%

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Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA

et al. 2021

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In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper presents the flexible placement of spare core onto Torus topology-based NoC design by considering core faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing algorithm, runtime fault injection model, and fault-tolerant placement of spare core onto Torus topology using an FPGA. Experiments have been done by taking different multimedia and synthetic application benchmarks. This has been done in both static and dynamic simulation environments followed by hardware implementation. In the static simulation environment, the experimentations are carried out by scaling the network size and router faults in the network. The results obtained from our approach outperform the methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size, our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of the proposed approach over the approaches presented in the literature.

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Section: Related Workmentioning

confidence: 99%