Total ionizing dose effect on 2-D array data transfer ICs designed and fabricated by 0.18 μm CMOS technology

Abstract

Circuits for CMOS two-dimensional (2-D) array data transfer are indispensable for applications such as space and nuclear fields. Issues include to be operated with higher speed, lower power, fewer size penalty and radiation hardness. To meet these requirements, two kinds of CMOS 2-D array data transfer circuits, such as a shift register type and a memory access type, are proposed and fabricated by the standard 0.18-µm CMOS process technology. In the both types, 16 µm pitch, 8×124 array data transfer operations were realized with data rate of more than 1 Gb/s. Furthermore, we conducted 60Co γ-ray irradiation experiments on those circuits. The current consumption ratio of the shift register type to the memory access type ranges from 150 to 200% as the dosage increases. The result indicate that the memory access type has better radiation hardness at 1 Gb/s than that of the shift register type.

Design and fabrication results of Z-gate layout MOSFETs for radiation hardness integrated circuit

“…Figure 5 shows the setup of the irradiation experiments. 31) The irradiation room and the measurement room were separated by concrete, so measurements were conducted by using a 10 m long coaxial cable through the wall. The evaluation board was placed at about 10 cm from the 60 Co γ-rays source.…”