Total Ionizing Dose Effects of 55-nm Silicon-Oxide-Nitride-Oxide-Silicon Charge Trapping Memory in Pulse and DC Modes

Li, Mei; Bi, Jinshun; Xu, Youqian; Li, Bo; Xi, Kai; Wang, Haibin; JingLiu,; Jinli,; Ji, Liangliang; Luo, Li; Liu, Ming

doi:10.1088/0256-307x/35/7/078502

Cited by 11 publications

(4 citation statements)

References 19 publications

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“…In the future, we intend to extend the model to include other floating gate structures, such as: (i) an oxide-nitrideoxide (ONO) interpoly oxide [15]- [17], (ii) a trap-rich dielectric as trapping layer, as in silicon-oxide-nitrideoxide-silicon (SONOS) charge trapping memories [22]- [23], and (iii) a floating gate that extends over a field oxide for increasing sensitivity in dosimetry applications [7].…”

Section: Discussionmentioning

confidence: 99%

Numerical modeling of radiation-induced charge loss in CMOS floating gate cells

Salomone

Garcia-Inza²,

Carbonetto³

et al. 2021

Elek.

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Mediante un modelo numérico desarrollado recientemente y basado en principios físicos, se estudia la respuesta a la radiación de celdas de compuerta flotante programadas/borradas. El rol que juega la captura de carga en los óxidos en el desplazamiento total de la tensión umbral con la dosis es debidamente evaluado a través de la variación de la tasa de captura de los huecos generados por radiación. Se considera un modelo analítico simplificado y se discuten sus limitaciones.

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Section: Discussionmentioning

confidence: 99%

Numerical modeling of radiation-induced charge loss in CMOS floating gate cells

Salomone

Garcia-Inza²,

Carbonetto³

et al. 2021

Elek.

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“…After 10 Mrad(Si) irradiation, the substrate electrode of device D is applied a pulse with different durations up to 7.5 μs and the same amplitude of 15 V, which is similar to the programming in SONOS devices [26][27]. The I-V characteristics and distribution of trapped charge of device D are obtained with respect to different pulse durations.…”

Section: Simulation Methodologymentioning

confidence: 99%

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Yan

et al. 2020

IEEE Access

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Based on 22 nm ultrathin-body fully depleted silicon-on-insulator (UTB-FDSOI) transistors, we propose a novel structure of buried insulator layer aiming at total ionizing dose (TID) effects mitigation. Using technology computer-aided design (TCAD) tools, we focus on the influences of UTB-FDSOI devices with different structures and parameters on TID effects, such as buried oxide (BOX) layer thickness, buried Si3N4 layer, and electron traps. First, we construct four types of UTB-FDSOI N-type metal-oxide semiconductor (NMOS) devices numerically, in which the novel device features a buried silicon-oxidenitride-oxide-silicon (SONOS) structure. Then, the transfer characteristics and trapped charge distribution of these devices are studied under different irradiation doses. It is known that a thinner BOX layer could lead to slighter TID effects, and the buried nitride layer and the electron traps could reduce the TID-induced leakage current (Ioff). Employing these optimization structures for TID effects hardness, the innovative transistor shows much better resistance against TID effects compared to the conventional FDSOI transistors. In addition, the threshold voltage of the novel device could be increased by applying appropriate bias conditions, similar to those of programming SONOS memory, so that the Ioff caused by TID irradiation further decreases. These results provide useful guidance for designers to achieve TID effects mitigation of SOI devices.

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“…Based on the silicon-oxide-nitride-oxide-silicon (SONOS) chargetrapping technology, the previously mentioned bottleneck problems could be effectively restrained and solved. The SONOS devices have a separate charge storage capacity with lower operation voltage, better endurance/retention performance, and compatibility with the CMOS process [10,11]. In the SONOS structure, an amorphous nitride layer rich in deeplevel traps is utilized to store electrons and holes.…”

Section: Introductionmentioning

confidence: 99%

Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

Cao

Tian

Majumdar

et al. 2021

Semicond. Sci. Technol.

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A novel vertical tunnelling field-effect transistor (TFET) based on silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device, named as VT-SONOS, is proposed and investigated using TCAD simulations. Different from traditional planar TFET-based SONOS memory, the VT-SONOS device is programmed via band-to-band tunnelling for vertical pocket and Fowler–Nordheim tunnelling for both pocket/bottom oxide (OXb) and channel/OXb regions, which leads to a steeper subthreshold swing (SS) and a larger on-state current (I ON). The device structure is constructed using Sentaurus TCAD tools, and I D–V G characteristics were extracted using TCAD tools. Obtained SS value is 102.09 mV dec−1, while the I ON was 3.02 × 10−4 A. The memory window was 2.95 V, showing more dependence on programming pulse height (V gp) than erasing pulse height (V ge). Furthermore, 10-year retention characteristics were studied to investigate critical reliability issue. About 60% of the initial trapped charges remained in the device after unbiased 3.15 × 108 s (10 years) storage.

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Total Ionizing Dose Effects of 55-nm Silicon-Oxide-Nitride-Oxide-Silicon Charge Trapping Memory in Pulse and DC Modes

Cited by 11 publications

References 19 publications

Numerical modeling of radiation-induced charge loss in CMOS floating gate cells

Numerical modeling of radiation-induced charge loss in CMOS floating gate cells

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

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