Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

Lu, Yuanlin; Agrawal, Vishwani D.

doi:10.1109/vlsi.2008.29

Cited by 3 publications

(2 citation statements)

References 16 publications

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“…A circuit engineer should be ready to face the challenge and be able to come up with the optimum design of the circuit. Simultaneously the inconsistent surge in various important technical characteristics might considerably upset the formulation and attainment of correct and least power consumed ICs in nanometer arrangement [11]. Gate Sizing Optimization is crucial to obtain timing closure and minimize the power dissipation of integrated circuits [12].…”

Section: Introductionmentioning

confidence: 99%

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Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

Maddileti¹,

Govindarajulu²,

Sivappagari³

2020

IJACSA

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Low Power Dissipation is an emerging challenge in the current electronics industry. Area shrinking has found the most prominent place and is the foundation of every constricted size in the utilization of CMOS circuits in Integrated Circuit Manufacturing. Functionality in terms of rapidity, dissipation of power, etc. are strongly influenced by the dimensions of transistors in many CMOS Integrated Circuits. The significant formulation parameters in CMOS circuit design to perform optimization of the above-mentioned parameters, and various techniques were projected earlier to a maximum extent possible. Latency, Power, and Dimension are significant parameters in the design of CMOS based IC design. Most analog circuit reduction in terms of size as parameter typically describes solitary or many objectives-controlled optimization issues. The eminent challenges with regards to size and power dissipation can be described as problems that are typically encountered under certain conditions. In this study, the design of a two-stage CMOS Differential Amplifier applying the nature-inspired Grey Wolf Algorithm for optimizing the area and power is utilized. To enhance the formulation terms concerning important considerations such as the amount incurred, strength, and functionality; a computerized formulation approach is used. This formulated design proposal will meet specifications such as positive and negative Slew Rate, Unity Gain Bandwidth and Phase Margin, etc. Chaos theory can be induced into the Grey Wolf Optimization Algorithm (CGWO) with the help of speeding global convergence metric i.e. Speed. The results obtained from CGWO are then analyzed with the functionality of other prevailing optimization techniques employed in the analog circuit sizing. Depending on the investigations, CGWO functions reduce the dimensions of the circuit and analyze the prevailing techniques by achieving a healthier rate of convergence and power dissipation with low value.

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Section: Introductionmentioning

confidence: 99%

“…second Stage gain is obtained as in(11),(12), (the third Transistor is calculated that is equal to the fourth transistor to determine and meet the upper Limit of ICMR as shown in(15) and(16).…”

mentioning

confidence: 99%

Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

Maddileti¹,

Govindarajulu²,

Sivappagari³

2020

IJACSA

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Design configuration selection for hard-error reliable processors via statistical rules

Zhang

Duan

Bin

et al. 2014

Microprocessors and Microsystems

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Variable Input Delay CMOS Logic for Low Power Design

Raja

Agrawal

Bushnell

2009

IEEE Trans. VLSI Syst.

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Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. We propose a new gate design that has different delays along various input to output paths within the gate. This is accomplished by inserting selectively sized "permanently on" series transistors at the inputs of the logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementation of a digital circuit. Applying a previously described linear programming method to the c7552 benchmark circuit, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. All circuits had the same overall delay. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on non-critical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.

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Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

Cited by 3 publications

References 16 publications

Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

Design configuration selection for hard-error reliable processors via statistical rules

Variable Input Delay CMOS Logic for Low Power Design

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