Toward large-scale access-transistor-free memristive crossbars

Ghofrani, Amirali; Lastras-Montaño, Miguel Angel; Cheng, Kwang-Ting

doi:10.1109/aspdac.2015.7059067

Cited by 12 publications

(8 citation statements)

References 29 publications

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“…Unit RS memory cells should be integrated in a crossbar‐structured parallel matrix with bit and word line interconnections to realize a resistive random access memory (RRAM) for fully functional memory operations . In this case, it is crucial to minimize the leakage current flowing through neighboring cells since this causes undesirable electrical interference, readout margin degradation, and additional power consumption . Merced‐Grafals et al demonstrated the 1 transistor‐1 resistor (1 T‐1 R) array of TaO x ‐based memristors.…”

Section: Inorganic Resistive Switching Memoriesmentioning

confidence: 99%

Unconventional Inorganic‐Based Memristive Devices for Advanced Intelligent Systems

Sung

Kim

et al. 2019

Adv Materials Technologies

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The latest progresses in software engineering such as cloud computing, big data analysis, and machine learning have accelerated the emergence of advanced intelligent systems (AIS). However, the current computing system has significant challenges in dealing with unstructured data (e.g., image, voice, physiological signals) because the von‐Neumann bottleneck induces latency and power consumption issues. Neuromorphic computing, which imitates the behaviors of neuron and synapse within the biological neural network, is considered a promising solution beyond von‐Neumann architecture, since its collocated structure of processor and memory enables parallel processing of unstructured data with remarkable efficiency. Memristors are considered as next‐generation nonvolatile memory devices due to fast speed, low power, and excellent scalability. However, a low reliability and leakage current issues remain as obstacle to the commercialization of memristors. Memristive devices have been widely investigated as a strong candidate for artificial synapses since their resistance modulation characteristics under electrical stimulus are analogous to the plasticity of the brain synapse. Although emulation of synaptic behavior by single memristor cells is demonstrated by many researchers, the development of fully functional memristive neural network requires further investigations. This paper introduces the recent advances and developments in the field of inorganic‐based unconventional memristive devices for future AIS applications.

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Section: Inorganic Resistive Switching Memoriesmentioning

confidence: 99%

Unconventional Inorganic‐Based Memristive Devices for Advanced Intelligent Systems

Sung

Kim

et al. 2019

Adv Materials Technologies

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“…From Figure 2 we could extract the minimum voltage amplitude, V abs , able to achieve a correct writing operation within t op s for all working temperatures within the considered range. Should there not be any non-desirable counter effects [25], the voltage amplitude V a bs could be employed satisfying the writing requirements in the whole temperature range. However, using V a b s as writing amplitude no matter the circuit temperature would raise two major disadvantages: not only would the power consumption be increased, but also the use of an amplitude larger than the required would lead to behavioral problems.…”

Section: Overcoming Rram System Limitationsmentioning

confidence: 99%

Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges

García‐Redondo

Royer

López‐Vallejo

et al. 2017

IEEE Trans. VLSI Syst.

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Abstract-Resistive switching memories (RRAM) are an attractive alternative to non-volatile storage and non-conventional computing systems, but their behavior strongly depends on the cell features, driver circuit and working conditions. In particular, the circuit temperature and the writing voltage scheme become critical issues, determining resistive switching memories performance. These dependencies usually force a design time trade-off among reliability, device endurance and power consumption, and therefore imposing non-flexible functioning schemes and limiting the system performance. In this paper we present a writing architecture that ensures the correct operation no matter the working temperature, and allows the dynamic load of application oriented writing profiles. Thus, taking advantage of more efficient configurations, the system can be dynamically adapted to overcome RRAM intrinsic challenges. Several profiles are analyzed regarding power consumption, temperature-variations protection and operation speed, showing speed-ups near to 700 x compared against other published drivers.

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“…Lithography and leakage-limited physical scaling and material dependent read/write voltage of electrical scaling are some of the issues plaguing today's non-volatile memories (NVMs) [1]. In recent years, several emerging memory technologies such as ReRAM [2,17], phase change memories [3], and spin-transfer torque magneto-resistive memories [4] have been under study to overcome these issues and Memristor technology has shown a lot of potential as a candidate for the next generation of non-volatile memory. Rather than replacing CMOS with these nascent technologies, a symbiotic approach utilizing the favorable properties of memristive devices, such as high density, fast switching and high endurance [5], could extend nanoscale memories beyond their current limitations.…”

Section: Introductionmentioning

confidence: 99%

A configurable CMOS memory platform for 3D-integrated memristors

Payvand

Madhavan

Lastras-Montaño

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Memristors are emerging as powerful nanoscale devices for diverse applications, such as high-density memories and neuromorphic applications. However, this nascent technology requires considerable advancement before this vision is realized. We present a highly configurable CMOS interface chip which enables the characterization of on-chip memristors, especially for memory applications. The chip was fabricated in On-Semi 3M2P 0.5 µm occupying 2×2 mm 2 . The chip design allows for post-CMOS fabrication of memristors. The interface between the memristor and the CMOS circuitry was provided via a top metal contact. The chip was designed to support an areadistributed interface decoupling CMOS pitch and memristor pitch, enabling high-density memristor integration. Measurement results on post-CMOS fabricated Ag/SiO 2 /Pt memristive devices are reported. Though we have shown the results from one memristive material stack, thorough chip characterization demonstrates the versatility of the chip enabling its use with a wide variety of materials stacks.

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Toward large-scale access-transistor-free memristive crossbars

Cited by 12 publications

References 29 publications

Unconventional Inorganic‐Based Memristive Devices for Advanced Intelligent Systems

Unconventional Inorganic‐Based Memristive Devices for Advanced Intelligent Systems

Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges

A configurable CMOS memory platform for 3D-integrated memristors

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