Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity

Abstract

Hardware Trojans (HT) are small circuits intentionally designed by an adversary for harmful purposes. These types of circuits are extremely difficult to detect. An HT often requires some specific signals to activate which is almost impossible to discover. For this reason, test generation for side channel analysis has gained significant attraction in recent times which does not require HT activation. Such test generation techniques aim to generate a large amount of switching activity inside the HT circuit, increasing transient current measurement. However, such methods suffer from either long runtime or reliable results. In this work, a test generation technique is proposed based on the relative switching activity of the circuit to overcome the limitations of the existing works. Initially, the proposed technique measures the impact of each input on rare nets individually using random vector simulation. Potent inputs are selected to obtain a new set of test vectors that provides high relative switching inside a circuit. The proposed method is applied on 11 different ISCAS and 3 ITC 99 benchmark circuits. Experimental results endorse the efficacy of the proposed method outperforming traditional hamming distance-based re-ordering techniques (up to 20x) while requiring a small run-time.

A Boundary Scan Test Vectors Optimization Method Based on Improved GA-AO* Approach Considering Fault Probability Model

“…This paper treats the 13 parameters in F(i) as a vector B k , and each B k is treated as an individual of the genetic algorithm. The fitness function of B k is shown in Equation (19).…”

“…Step 3 Average all the elements in the Equation (1) except diagonal elements and set the result as P. For the circuit with n networks, randomly generate (19).…”