Towards a Dynamic and Reconfigurable Multicore Heterogeneous System

Souza, Jeckson Dellagostin; Carro, Luigi; Rutzig, Mateus Beck; Beck, Antonio Carlos Schneider

doi:10.1109/sbesc.2014.21

Cited by 5 publications

(4 citation statements)

References 14 publications

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“…Recently (2016 onwards), DySER has been the focus of the FPGA-overlay scene (see Section IV-G). Other similar work to DySER that integrates CGRA-like structures into processing cores with various goals includes CReAMS/HARTMP [79], [80] (applies dynamic binary translation) or CGRA-sharing [81] (conceptually similar to what AMD Bulldozer architecture [82] and UltraSPARC T1/T2 did with their floating-point units).…”

Section: B Modern Coarse-grained Reconfigurable Architecturesmentioning

confidence: 99%

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

2020

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Section: B Modern Coarse-grained Reconfigurable Architecturesmentioning

confidence: 99%

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

2020

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“…Concerning how the resources of the reconfigurable architecture are distributed into a multi-core processor, there are two types of CGRA organization: homogeneous and heterogeneous. In the first organization, the reconfigurable resources are the same to all cores [11] [2]. In the latter organization, the number of reconfigurable resources may be different for each core [3].…”

Section: Related Workmentioning

confidence: 99%

“…CReAMS [2] is a homogeneous CGRA for multi-core processor. It proposes a multi-core system where each core is a DAP (Dynamic Adaptative Processor).…”

Section: Related Workmentioning

confidence: 99%

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A Partially Shared Thin Reconfigurable Array For Multicore Processor

Carlos¹,

Silva²,

Jacobi³

2019

Anais Estendidos Do IX Simpósio Brasileiro De Engenharia De Sistemas Computacionais (SBESC Estendido 2019)

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Reconfigurable architectures have been widely used as single core processor accelerators. In the multi-core era, however, it is necessary to review the way that reconfigurable arrays are integrated into multi-core processor. Generally, a set of reconfigurable functional units are employed in a similar way as they are used in single core processors. Unfortunately, a considerable increase in the area ensues from this practice. Besides, in applications with unbalanced workload in their threads this approach can lead to a inefficient use of the reconfigurable architecture in cores with a low or even idle workload. To cope with this issue, this work proposes and evaluates a partially shared thin reconfigurable array, which allows to share reconfigurable resources among the processor's cores. Sharing is performed dynamically by the configuration scheduler hardware. The results shows that the sharing mechanism provided 76% of energy savings, improving the performance 41% in average when compared with a version without the proposed reconfigurable array. A comparison with a version of the reconfigurable array without the sharing mechanism was performed and shows that the sharing mechanism improved up to 11.16% in the system performance.

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