Towards a flexible network processor interface for rapidIO, hypertransport, and PCI-Express

This paper presents a technology independent and * posted -request that requires no response; open source HyperTransport (HT) tunnel. HT is a high * non-posted -request that requires a response;performance and low latency chip-to-chip interconnect * response -reply to a non-posted request.standard. Various aspects of the architecture are presented, ranging from how functionality is spread over clock domains The aim of the research is to obtain a reusable HT to the means of implementing a packet reordering algorithm.technology core that can either be enriched with features or The analysis of synthesis results provides a better insight of the simplified, in order to explore tradeoffs relative to system complexity of various features and what limits the level switch fabrics design and implementation. A tunnel can performance of the HT tunnel. be simplified to become a cave, and many of its parts could be reused in the design of a switch. The developed tunnel has been verified using a bottom-up approach and is open

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Architecture of a hypertransport tunnel

Castonguay

Savaria

2006 IEEE International Symposium on Circuits and Systems

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Towards a flexible network processor interface for rapidIO, hypertransport, and PCI-Express

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References 14 publications

Architecture of a hypertransport tunnel

Architecture of a hypertransport tunnel

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