1992
DOI: 10.3233/jhs-1992-1401
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Towards a Gigabit IP Router

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Cited by 34 publications
(5 citation statements)
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“…Such an architecture has the drawback of poor utilization because all the processors are hardly ever saturated, as the load is almost never evenly distributed over the inputs and does not always reach the nominal rate. Parallel router architectures [2], [9] are based on a pool of parallel processors, located remotely from the inputs, with all of the processors being able to perform the data path processing tasks. Packets may be buffered at the inputs, and relevant fields of the packet (for example, the packet header) are being sent to the pool for resolution.…”
Section: A Router Architecturementioning
confidence: 99%
“…Such an architecture has the drawback of poor utilization because all the processors are hardly ever saturated, as the load is almost never evenly distributed over the inputs and does not always reach the nominal rate. Parallel router architectures [2], [9] are based on a pool of parallel processors, located remotely from the inputs, with all of the processors being able to perform the data path processing tasks. Packets may be buffered at the inputs, and relevant fields of the packet (for example, the packet header) are being sent to the pool for resolution.…”
Section: A Router Architecturementioning
confidence: 99%
“…In the second generation IP routers, improvement was introduced to increase the system throughput by distributing the packet forwarding operations by using multiple processors with on-demand lookup route caching. However, the frequent changes in network topology in the core of the Internet caused the cache entries to be invalidated frequently, resulting in smaller hits [ 22 ]. The third generation of routers introduced a hardware-forwarding engine and replaced shared bus by a high-speed crossbar switch with the aim to achieve higher throughput [ 23 ].…”
Section: Related Workmentioning
confidence: 99%
“…Another bus-based multiple processor router architecture is described in Reference [37]. Multiple forwarding engines are connected in parallel to achieve high packet processing rates as shown in Figure 6.…”
Section: Architectures With Multiple Parallel Forwarding Enginesmentioning
confidence: 99%
“…The CPU subsystem can communicate with all other network interfaces through the exchange of coded messages across the switch fabric (or on a separate control bus [37,40]). IP datagrams Figure 9.…”
Section: Non-critical Data Path Processing (Slow Path)mentioning
confidence: 99%