Towards a high-level synthesis of reconfigurable bit-serial architectures

Rettberg, Achim; Dittmann, Florian; Zanella, M.; Lehmann, T.

doi:10.1109/sbcci.2003.1232810

Cited by 8 publications

(8 citation statements)

References 6 publications

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“…It consists of about 12,000 lines of C. The theory of its operation has been described in several papers cited by [3,5,10]. Other tools [1,4,[6][7][8] use similar one-to-one mappings to one-hot controllers; VITO has the advantage of being a simple, freely available, opensource tool based on a widely-used HDL.The basic idea is to perform superficial lex/yacc parsing of Verilog source code and to identify implicit-style state machines. The term implicit-style is used to describe placing state boundaries in a behavioral flow, in contrast to explicitstyle, which views the state machine in terms of a nextstate function.…”

Section: Vitomentioning

confidence: 99%

Bitstream Efficiency of Field Programmable One-Hot Arrays

Arnold

Vouzis

Cho

2010

2010 IEEE Computer Society Annual Symposium on VLSI

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Field Programmable One-Hot Arrays (FPOHAs) have simple cells which are suitable to implement control-rich algorithms, where one-hot encoding is preferred. We present the cell design for the FPOHA and describe a modified open-source one-hot tool, known as Verilog Implicit To One-hot (VITO), to synthesize one-hot designs into FPOHA configurations without global optimization. We compare the bitstream sizes for FPOHAs and FPGAs using artificial benchmarks. In theory, optimal FPOHA layouts could have bitstream sizes half that of FPGAs. The observed FPOHA sizes synthesized from VITO may not be optimal, but are still often more efficient than FPGA sizes.

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Section: Vitomentioning

confidence: 99%

Bitstream Efficiency of Field Programmable One-Hot Arrays

Arnold

Vouzis

Cho

2010

2010 IEEE Computer Society Annual Symposium on VLSI

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“…Additionally, the fully interlocked pipeline allows the architecture to support multiple applications within one implementation. The architecture is described in more detail in [8,7].…”

Section: Fig 2 Example Data Packetmentioning

confidence: 99%

Low–Level Space Optimization of an AES Implementation for a Bit–Serial Fully Pipelined Architecture

Weber

Rettberg

2009

IFIP Advances in Information and Communication Technology

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Abstract.A previously developed AES (Advanced Encryption Standard) implementation is optimized and described in this paper. The special architecture for which this implementation is targeted comprises synchronous and systematic bit-serial processing without a central controlling instance. In order to shrink the design in terms of logic utilization we deeply analyzed the architecture and the AES implementation to identify the most costly logic elements. We propose to merge certain parts of the logic to achieve better area efficiency. The approach was integrated into an existing synthesis tool which we used to produce synthesizable VHDL code. For testing purposes, we simulated the generated VHDL code and ran tests on an FPGA board.

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“…In addition, the fully interlocked pipeline allows for extending the architecture to support multiple applications within one implementation. The architecture is described in more detail in [13,14,12,3,4].…”

Section: Mact Architecturementioning

confidence: 99%

Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture

Giefers

Rettberg

2006

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design

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In this paper, we present an approach for low-power driven synthesis based on local frequency/voltage scaling. During the scheduling phase of the High-Level Synthesis (HLS) the design is partitioned into different frequency/voltage islands. Operators within these islands, are encapsulated by wrappers to ensure correct dataflow between the islands. A wrapper consists of a clock generator and input-and output ports. The local clocks are calculated by dividing the global clock signal. With the developed wrappers we are able to automatically integrate local frequency/voltage scaling for our target architecture by our HLS tool. As an example we implement the inverse discrete cosine transformation (IDCT).

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Towards a high-level synthesis of reconfigurable bit-serial architectures

Cited by 8 publications

References 6 publications

Bitstream Efficiency of Field Programmable One-Hot Arrays

Bitstream Efficiency of Field Programmable One-Hot Arrays

Low–Level Space Optimization of an AES Implementation for a Bit–Serial Fully Pipelined Architecture

Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture

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