Towards a many-core architecture for HPC

Abstract

Many-core architectures are a current avenue of research, seeking alternative higher efficiency computing, and HPC is one domain which may benefit most from such a model. While at an initial prototyping stage we present here the design of a MIMD many-core processor, Fynbos and, considering the problems of programmability, an autoparallelising Fortran pipeline. Our initial operating results demonstrate functionality, and the effectiveness of the compiler as the system efficiency increases with problem size in a test case multi-body simulation. The test case also serves to highlight system weaknesses. We conclude that the demonstration offers sufficient motivation for the future work discussed.

Job migration in HPC clusters by means of checkpoint/restart

“…The evolution of HPC hardware follows a clear path: an increasingly large number of processing units per cluster. For many years now, miniaturization and technical improvements have provided a larger number of resources, with limits of the technology and the nature of applications orienting processor design into simple ones with an increasing number of cores [1,2]. Moreover, as performance varies over computers generations and characteristics, it is common to see heterogeneous clusters composed by resources with different performance, and even islands of clusters with notable differences in network connection among the nodes (see, for example, the TOP500 list at https://www.top500.org/).…”