Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators

Abstract

Multi-/Many-core architectures are emerging as scalable, high-performance and energy-efficient computing platforms suitable for a variety of application domains from edge to cloud computing. Recently, the appearance of RISC-V open-source ISA creates new possibilities to develop customized computing platforms with high savings in the non-recurring engineering costs. Moreover, the current trends toward open-source hardware frameworks are aimed to reduce design time and cost for complex system-on-chip architectures. Therefore, modularity and re-usability of hardware components are major challenges for flexible hardware architectures. The motivation behind this work is to introduce a modular cluster-based many-core architecture for FPGA accelerators that is re-usable and flexible tailored to implement different many-core taxonomies with less design time and costs by using regular and replicated sets of computing, memory, and interconnection blocks. The proposed many-core architecture is built using multiple processing clusters coupled with a NoC for communication which allows a high degree of design scalability. The processing cluster inside features a configurable multi-core architecture consisting of multiple RISC-V processing elements (PE) tightly coupled with a bus-based interconnection for intra-cluster communication using parameterized scratchpad shared memory. Each PE features a single RISC-V core with a tightly coupled parameterized scratchpad local memory and generic AXI interface. Evaluation results demonstrate that the proposed architecture features a scalable computing performance of 501 MOp/s for 4 clusters and 878 MOp/s for 8 clusters. Moreover, a scalable memory bandwidth up to 4.3 GB/s is achieved for 9 clusters with a power consumption of 1.4 W per cluster utilizing 7.7% of on-chip memory resources. The many-core architecture is implemented and evaluated on Xilinx Virtex Ultrascale+ with the feature of changing the architecture configurations during run-time using dynamic and partial reconfiguration which provides more flexibility and re-usability.INDEX TERMS Many-core architecture, parallel computing, RISC-V, network-on-chip (NoC), field programmable gate array (FPGA), reconfigurable computing.

ManyGUI: A Graphical Tool to Accelerate Many-core Debugging Through Communication, Memory, and Energy Profiling

“…Focusing on an updated classification, we consider only recent works, dating not more than 5 years ago (from 2017 on). Older platforms classifications can be found in [1,7,14]. The 2 nd column addresses the language used to model the platforms.…”

“…The 3 rd column classifies works by detailing how the computation is implemented. Noticeably, RISC-V was received considerable attention from research, resulting in the majority of the works, which either adopt RISC-V cores exclusively [2,6,7] or use it in an on-chip heterogeneous fashion [4,8,15]. Another observed aspect is that many-cores are increasingly adopting accelerators to reach energy efficiency in complex applications, specifically to support machine learning [4,12,13,15].…”

“…Few architectures adopt purely distributed system [6,11,14]. Most systems use a hybrid shared memory system, which includes a private memory (L1 or scratchpad) with a logically shared but physically distributed last level shared memory [1,2,7,12,15]. Such hybrid systems are suitable to many-core since a centralized shared memory is not scalable for a high number of tiles [1].…”

“…Other works [8,9,15], argue that cache coherence protocols are not scalable for many-cores due to their high cost in terms of synchronization overhead and energy consumption observed, specifically, for streaming data-flow applications [15]. Instead, the alternative is to rely upon software-managed scratchpad memory close to each CPU, with the communication among CPUs initialized by software [1,7,8,14,15]. Some designs cluster the cores and assign a shared memory for each cluster [1,7,8,13].…”

HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing

“…Existing research platforms do not meet these requirements in their entirety. Many provide a custom accelerator on programmable logic [15], [16], and some even couple the accelerator to a host processor that runs an operating system [17], [18]. HEROv1 [19] provides software stack and compiler that enable the evaluation of real-world applications on a mixed-instruction set architecture (ISA) computer, but it fundamentally restricts host and accelerator to use the same data model (e.g., 32-bit).…”