Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation

Abstract

Nanoelectronic devices are considered to be the computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. However, the imperfect bottom-up self-assembly fabrication leads to excessive defects that have become a barrier for achieving reliable computing. In addition, transient errors continue to be a problem. The massive parallelism rendered by nanoscale integration opens up new opportunities but also poses challenges on how to manage such massive resources for reliable and high-performance computing. In this paper, we propose a nanoarchitecture solution to address these emerging challenges. By using dynamic redundancy allocation, the massive parallelism is exploited to jointly achieve fault (defect/error) tolerance and high performance. Simulation results demonstrate the effectiveness of the proposed technique under a range of fault rates and operating conditions.

Analysis and Design of an Abft and Parity-Checking Technique in High Performance Computing Systems

“…1À6 Coding techniques based on ABFT have already been proposed for various computations such as matrix operations, FFT, 13 QR factorization, 14À18 and singular value decomposition. 14,15 Real number codes such as the Checksum and Weighted Checksum codes have been proposed for fault-tolerant matrix operations such as matrix transposition, addition, multiplication and matrixÀvector multiplication. 1À5 Application of these techniques in processor arrays and multiprocessor systems has been investigated by various researchers.…”