Towards adaptive balanced computing (ABC) using reconfigurable functional caches (RFCs)

Kim, Huesung

doi:10.31274/rtd-180813-13230

Cited by 4 publications

(32 citation statements)

References 51 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The mechanism of computation in RFC and the functioning of the ABC micropro cessor are discussed in detail in [42]. Here, we present a brief overview of the operation of the ABC architecture.…”

Section: Architecture Simulator For Abc Implementationmentioning

confidence: 99%

“…The performance of the ABC architecture is assessed based on the number of cycles it takes to execute each application as compared to a superscalar processor with a con ventional cache. The performance of the ABC processor has been discussed extensively in [42] with varying cache parameters like cache size, line size and associativity. A set of those results, for a 32KB 4-way with a line size of 32B, for various media applications are shown in Table 4.1.…”

Section: Performance Of Abc Processormentioning

confidence: 99%

“…Hence, there is scope for an increase in the cache miss rate. For this reason, [42] gives an elaborate discussion on the increment in the cache miss rate and increased accesses to L2 unified cache, and the subsequent impact on the performance of the processor. In Figure 4.9, each simulation result data set, for a particular cache structure The MPEG2 encode application has a smaller fraction (6.89% as shown in Figure 4.9)…”

Section: Performance Of Abc Processormentioning

confidence: 99%

“…The effective address for the r/c J to _ml/2 instruction is calculated using the existing datapath and passed to the corresponding instruction in IBUF, not in LSQ. The details of mechanism to support out-of-order update (load) of input data in IBUF are discussed extensively in [42]. If no slot in IBUF is available, the following instructions including conventional instructions fetched from memory are stalled until IBUF is again available.…”

Section: Execution Stagementioning

confidence: 99%

“…However, with a smaller cache memory size, the inadequacy would be that when the RFC is configured with the core function, the cache capacity for the other computations in the application would be reduced further. The direct-mapped cache for mpeg2encode increases the number of execution cycles by about 16.1% for 16KB and 7.2% for 32KB due to the significant increase in cache misses [42]. Thus the performance degradation in using RFC is caused by the reduction in cache capacity to half and in associativity to direct-mapped, when the RFC is configured with DCT/IDCT during the running of the mpeg2encode application.…”

Section: Rfc Configuration Schemesmentioning

confidence: 99%

See 4 more Smart Citations

On-chip adaptive components for balanced computing

Sangireddy¹,

Somani²

View full text Add to dashboard Cite

The data array in other modules is similarly arranged 62 4.3 One tap of FIR filter implemented in four rows of LUTs in an RFC module with 8 columns of LUTs. The blank LUTs do not participate in computation mode, but function normally in memory mode 4.4 Two successive processing elements (PEs) for DCT/IDCT, imple mented in four rows of LUTs in an RFC module with 8 columns of LUTs. The blank LUTs do not participate in computation mode, but function normally in memory mode 4.5 Access time, at 0.8 micron CMOS technology, in conventional cache and the RFC for Convolution algorithm implementation. x-axis indicates the cache associativity from 2-to 32-way, for each cache size in KB 4.6 Energy dissipation, at 0.8 micron CMOS technology, in conventional cache and the RFC for Convolution algorithm implementation. x-axis indicates the cache associativity from 2-to 32-way, for each cache size in KB 4.7 rfc instructions for loading and storing "word" type of data ... 4.8 State transition for the RFC cache 4.9 Performance of ABC processor vs. base processor for a 32KB 4-way cache with a line size of 32B 4.10 Component power utilization in ABC processor vs. base processor for MPEG2 decode application. X 4.11 Component power utilization in ABC processor vs. base processor for MPEG2 encode application 86 4.12 Component power utilization in ABC processor vs. base proces sor for FIR application 4.13 Component power utilization in ABC processor vs. base proces sor for cjpeg application 88 4.14 Component power utilization in ABC processor vs. base proces sor for IIR application 4.15 Total power utilization in ABC processor vs. base processor using (a) Alpha processor model (b) Pentium-Pro model 90 5.1 Reconfigurable Functional Cache (RFC) organizations and ad dress mapping with (a) 4 cache modules (b) 16 cache modules.. 5.2 Normalized execution cycles in base processor without RFC and ABC processor with RFC, with varying cache organizations.. . 5.3 Distribution of core functions in MPEG applications 5.4 Variation of cache blocking factor with the fraction of core function. 5.5 Variation of cache blocking factor with speed-up in core function. 109 5.6 Normalized execution cycles in the base processor without RFC, and the ABC processor with different RFC configuration schemes. 5.7 Relative performance improvement in two RFC configuration schemes. 114 5.8 Architectural Design Space 6.1 Packet routing based on longest prefix matching mechanism.. . 6.2 Function / = %oZi + ^1^2 + ^2^0 represented as (a) Binary decision tree and (b) BDD 6.3 Binary decision tree for the sample routing table. Dotted nodes are redundant. 6.4 Binary decision tree for (a) (b) with all effective nodes assigned with output. Dotted nodes are redundant xi 6.5 BDDs for (a)N^Pi. (b)AWo 6.6 (a) Nodes with assigned NHP ports. (b),(c),(d),(e) Output bits assigned to each of the nodes in 4-bit binary encoding of NHP. Dotted nodes are redundant 6.7 CLB mapping in FPGA 6.8 (a) Binary decision tree representation of the modified routing table. Dotted nodes are redundant, (b)...

show abstract

Section: Architecture Simulator For Abc Implementationmentioning

confidence: 99%

Section: Performance Of Abc Processormentioning

confidence: 99%

Section: Performance Of Abc Processormentioning

confidence: 99%

Section: Execution Stagementioning

confidence: 99%

Section: Rfc Configuration Schemesmentioning

confidence: 99%

See 3 more Smart Citations