2018
DOI: 10.1016/j.jnca.2018.09.012
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Towards an FPGA-Accelerated programmable data path for edge-to-core communications in 5G networks

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Cited by 33 publications
(24 citation statements)
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References 26 publications
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“…The main architecture for prototyping is based on NetFPGA (10 Gbps) cards and the P4 programming language, following the SimpleSumeSwitch architecture [12]. The proposed architecture in this paper allows not only traffic parsing and classification b ased o n t he s olution p resented i n [13], but also applying QoS control to the multimedia especially video transmission over 5G networks. This QoS control is applied through a Representational State Transfer (REST) API, which allows selecting the priorities of the 5G network traffic processed by the NetFPGA.…”
Section: Key Technical Enablers and Innovationsmentioning
confidence: 99%
“…The main architecture for prototyping is based on NetFPGA (10 Gbps) cards and the P4 programming language, following the SimpleSumeSwitch architecture [12]. The proposed architecture in this paper allows not only traffic parsing and classification b ased o n t he s olution p resented i n [13], but also applying QoS control to the multimedia especially video transmission over 5G networks. This QoS control is applied through a Representational State Transfer (REST) API, which allows selecting the priorities of the 5G network traffic processed by the NetFPGA.…”
Section: Key Technical Enablers and Innovationsmentioning
confidence: 99%
“…This series of chips contains several GPU cores and several ARM CPU cores. Using container virtual machines installed in the ARM CPU, the master node can control and schedule GPU resources.FPGA resource nodes: This node provides FPGA computing resources for the system [41]. It is used for hardware acceleration in the fields of video/image processing, deep learning, gene detection, financial data analysis, and so on.…”
Section: System Frameworkmentioning
confidence: 99%
“…FPGA resource nodes: This node provides FPGA computing resources for the system [41]. It is used for hardware acceleration in the fields of video/image processing, deep learning, gene detection, financial data analysis, and so on.…”
Section: System Frameworkmentioning
confidence: 99%
“…In this solution, the authors use the dual Read/Write ports of the BRAM memory to process two search in every clock. Ricart-Sanchez et al [10] proposes a hardware-based data-path for 5G multitenant scenarios. Authors provide an exhaustive analysis in terms of performance, scalability and reliability of the datapath developed, however they do not present any security solution for 5G multi-tenant scenarios which has been the main motivation of this research work.…”
Section: Related Workmentioning
confidence: 99%