Towards an Optimized Architecture for Unified Binary Huff Curves

Abstract

Applying uni¯ed formula while computing point addition and doubling provides immunity to Elliptic Curve Cryptography (ECC) against power analysis attacks (a type of side channel attack). One of the popular techniques providing this uni¯edness is the Binary Hu® Curves (BHC) which got attention in 2011. In this paper we are presenting highly optimized architectures to implement point multiplication (PM) on the standard NIST curves over GF ð2 163 Þ and GF ð2 233 Þ using BHC. To achieve a high throughput over area ratio,¯rst of all, we have used a simpli¯ed arithmetic and logic unit. Secondly, we have reduced the time to compute PM through Double and Add algorithm. This is achieved by increasing the frequency of operation through a 2-stage pipelined architecture. The increase in clock cycles caused by consequent pipeline hazards is controlled through optimal scheduling of computations involved in PM. The synthesis results show that our designs can work up to a frequency of 377 MHz on Xilinx Virtex 7 FPGA. Moreover, the overall throughput/area ratio achieved through the adopted approach is up to 20% higher while comparing with available state-of-the-art solutions. J CIRCUIT SYST COMP Downloaded from www.worldscientific.com by MONASH UNIVERSITY on 04/22/17. For personal use only. A. R. Jafri et al. 1750178-2 J CIRCUIT SYST COMP Downloaded from www.worldscientific.com by MONASH UNIVERSITY on 04/22/17. For personal use only. Towards an Optimized Architecture for Uni¯ed Binary Hu® Curves 1750178-3 J CIRCUIT SYST COMP Downloaded from www.worldscientific.com by MONASH UNIVERSITY on 04/22/17. For personal use only. A. R. Jafri et al. 1750178-4 J CIRCUIT SYST COMP Downloaded from www.worldscientific.com by MONASH UNIVERSITY on 04/22/17. For personal use only.

Throughput/area optimised pipelined architecture for elliptic curve crypto processor

“…Previously, we have proposed a throughput/area processor for binary huff curves [21]. In this paper, we are targeting a pipelined architecture of ECC for those applications, where the throughput/ area is critical such as internet-based applications [16,17], cloud computing [18], and banking applications [19].…”

The Consumer Demand Estimating and Purchasing Strategies Optimizing of FMCG Retailers Based on Geographic Methods

“…The aim in data clustering is to group spatial data or multidimensional attribute data into several collections of clusters, and make the gap between different clusters as large as possible. In contrast, the differences between elements within the same class must be as small as possible [45]. The commonly used clustering algorithms include DBSCAN clustering algorithm and K-means clustering algorithm.…”

FPGA Based Crypto Processor for Elliptic Curve Point Multiplication (ECPM) Over GF(2233)

“…The performance of the entire crypto architecture is mainly depends upon its FF multiplier and inversion [17]. In recent research practices, the most commonly implemented multipliers are bit parallel [12], [17]- [19] and digit serial [10] and [20].…”

“…The performance of the entire crypto architecture is mainly depends upon its FF multiplier and inversion [17]. In recent research practices, the most commonly implemented multipliers are bit parallel [12], [17]- [19] and digit serial [10] and [20]. The bit parallel multipliers are used to achieve higher performances [18] whereas digit serial multipliers are used to achieve optimal throughput/area designs [20].…”

“…The bit parallel multipliers are used to achieve higher performances [18] whereas digit serial multipliers are used to achieve optimal throughput/area designs [20]. The bit parallel multipliers include, hybrid karatsuba multiplier, implemented in [12] and [18] and karatsuba Ofman multiplier, implemented in [17] and [19]. Moreover, digit serial multipliers can be implemented by varying digit sizes as implemented in [10] and [20].…”