Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Abstract

Deeply-scaled three-dimensional (3D) Multi-Processor Systemson-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However as process nodes shrink, temperature-dependent leakage dramatically increases, and thermal and power management becomes problematic. In this context, Integrated Flow Cell Array (FCA) technology, which consists of inter-tier microfluidic channels, combines onchip electrochemical power generation and liquid cooling of 3D MPSoCs. When connected to power delivery networks (PDN) of dies, FCAs provide an additional current compensating the voltage drop (IR-drop). In this paper, we evaluate for the first time how the IR-drop reduction and cooling capabilities of FCAs scale with advanced CMOS processes. We develop a framework to quantify the system-level impact of FCAs at technology nodes from 22𝑛𝑚 to 3𝑛𝑚. Our results show that, across all considered nodes, FCAs reduce the peak temperature of a multi-core processor (MCP) and a Machine Learning (ML) accelerator by over 22°C and 35°C, respectively, compared to off-chip direct liquid cooling. Moreover, the low operation voltages and high temperatures at advanced nodes improve up to 2× FCA power generation. Hence, FCAs allow to keep the IR-drop below 5% for both the MCP and ML accelerator, saving over 10% TSV-reserved area, as opposed to using a High-Performance Computing (HPC) MPSoC liquid cooling solution.

Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters

“…High channel temperatures increase the electrochemical reaction rate, effectively transforming heat into available power for high-performance 3D MPSoCs. As shown in [5] and [11], FCA-generated current can recover up to 20% voltage drop when augmenting an existing PDN. Alternatively, FCAs can also be employed to reduce the density of power delivery components (e.g., power TSVs) for a traditional PDN while abiding by a given voltage drop constraint.…”

“…As fan-based cooling struggles to maintain 3D MPSoC temperatures at acceptable levels, a high-performance direct liquid cooling solution using a cold plate has been proposed [10]. Nonetheless, such an approach requires large cold plate dimensions, low coolant temperatures, and costly materials to extract the high amount of heat generated by 3D MPSoCs [11]. Similar to FCA technology, inter-tier liquid cooling employs micro-channels etched in the silicon substrate of 3D MPSoC dies, through which a liquid is pumped, which absorbs the generated heat [12].…”

“…The transistors are typically sized to achieve 10nA/µm leakage per gate width for low and medium performance, and 20nA/µm leakage per gate width for high performance [35], at the reference temperature of 25°C. Then, this value increases exponentially with temperature [11]. Hence, the total leakage power of the GPU die for a temperature t GP U is calculated as follows:…”

Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

“…The FCAs are connected to the 3D MPSoC power grid through DC-DC voltage regulators, ensuring that they operate at their optimal voltage (enabling the maximal power generation) regardless of transient load changes in the chip [12]. As shown in [13] and [12], FCAs can reduce temperature by 50°C compared to traditional fan-based cooling, and recover up to 20% of voltage drop in the 3D PDNs. Consequently, FCAs provide an opportunity to increase the load of dies while mitigating the performance losses related to voltage drop and temperature.…”

“…The temperature map 𝑇 of each die is evaluated using 3D-ICE [15] when the power consumption profiles of the 3D MP-SoC computing dies correspond to the previously calculated power maps. (iii) The leakage map 𝑃 𝑙𝑒𝑎𝑘 is estimated for each computing die according to its thermal map 𝑇 , using the temperature and transistor leakage relationship that characterizes the specific CMOS technology [13]. Hence, the total power map is calculated as: 𝑃 𝑡𝑜𝑡𝑎𝑙 = 𝑃 𝑑𝑦𝑛 + 𝑃 𝑙𝑒𝑎𝑘 .…”