Towards Efficient Task Placement Selection on 2D Reconfigurable Devices

Abstract

Current 2D FPGA allows independent tasks to run concurrently without interfering with each other, which makes it confront task placement problem. Task placement consists of placement management and placement selection. Placement management manages all of the available locations on the FPGA while placement selection selects the proper location for each incoming task from the current available locations. Since we have proposed a Vertex-Scan (VS) algorithm for placement management that can efficiently find all free locations on the FPGA, this paper focuses on the problem of placement selection for tasks. A cost function based placement selection method is proposed that formalizes the influence of both time factor and space factor on the generation of fragmentation in FPGA. Simulations show that compared with the other methods, our method can achieve the lowest ratio of waiting tasks and waiting time. In addition, our methods advantages become more prominent especially in the circumstances of medium or smaller task sizes, and shorter time intervals.