Towards Fault-Tolerant Energy-Efficient High Performance Computing in the Cloud

Keville, Kurt; Garg, Rohan; Yates, David J.; Arya, Kapil; Cooperman, Gene

doi:10.1109/cluster.2012.74

Cited by 10 publications

(6 citation statements)

References 10 publications

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“…However, we studied the ATCCp behavior compared to coordinated checkpointing CCp used in [1], [16], [35] and independent checkpointing ICp used in [15], [28], [36]. The goal is proofing that our approach ensures a strong consistency with the minimum cost (like the CCp) and with the minimum overhead (like the ICp).…”

Section: Analysis and Comparative Studymentioning

confidence: 99%

“…The cloud provisions pools of computing resources as services via the internet using a pay-as-you-go price model that eliminates initial costly capital investments in hardware and infrastructure. Research and academic communities can leverage the benefit of the cloud price model for their computationintensive applications that traditionally run in HPC environments [34], [35], [36], [37] such as Amazon Web Services' HPC offering [38] or science cloud initiatives [39].…”

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confidence: 99%

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Adaptive time-based coordinated checkpointing for cloud computing workfl ows

Meroufel¹,

Belalem²

2014

SCPE

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Abstract. Cloud computing is a new benchmark towards enterprise application development that can facilitate the execution of workflows in business process management system. The workflow technology can manage the business processes efficiently satisfying the requirements of modern enterprises. Besides the scheduling, the fault tolerance is a very important issue in the workflow management. In this paper, we analyse and compare between some existing checkpointing strategies, then we propose a lightweight checkpointing adequate to the cloud computing and the workflows characteristics. The proposed strategy is an Adaptive Time based Coordinated Checkpointing ATCCp, it ensures a strong consistency without any synchronization. ATCCp uses the concept of soft checkpointing to minimize the storage time and it uses the VIOLIN topology to improve the checkpointing performances. According to the experimental results, our approach decreases the overhead and the SLA violations.

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Section: Analysis and Comparative Studymentioning

confidence: 99%

mentioning

confidence: 99%

Adaptive time-based coordinated checkpointing for cloud computing workfl ows

Meroufel¹,

Belalem²

2014

SCPE

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“…Checkpointing has a long history in HPC [7]- [10]. In 2012, a cluster of ARM CPUs was tested with respect to checkpointing as a basis for power-efficient HPC [11]. This used the more powerful ARM Cortex-A9 CPU, whereas the current Raspberry Pi Model B uses the less powerful ARM Cortex-A7.…”

Section: Checkpointing Using Dmtcpmentioning

confidence: 99%

Smart scene management for IoT-based constrained devices using checkpointing

Aïssaoui

Cooperman

Monteil

et al. 2016

2016 IEEE 15th International Symposium on Network Computing and Applications (NCA)

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Typical devices of the Internet of Things are usually under-powered, and have limited RAM. This is due to energy and cost concerns. Yet, IoT applications require increasingly complex programs with increasingly large amounts of data. In principle, an application could manage the increasing data within the limited RAM by saving and loading data from the file system as needed. But managing the use of RAM in this way is both timeconsuming and error-prone for the code developer. We propose instead a novel architecture in which different semantic scenes are implemented as independent operating system processes. As the need arises to switch from one scene to another, the currently running process, which represents the current scene, is checkpointed and a process representing the new scene is restarted from a checkpoint image. This solution employs checkpointing to provide a simpler framework for the end programmer, while at the same time resulting in higher performance. For example, experiments show that restarting an old process from a checkpoint image is about 25 times faster than starting a new process. When using an mmap-based optimization (deferring the paging in of virtual memory pages until runtime), restarting an old process is about 500 times faster. Overall, checkpoint and restart each execute in less than 0.2 seconds on a Raspberry Pi B.

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“…Edson et al compared the execution times, power consumption, and maximum instantaneous power between two clusters based on a Cortex-A9 PandaBoard and a Cortex-A8 BeagleBoard [26]. Keville et al [27] also performed early attempts for ARM benchmarking. They evaluated ARM-based clusters for the NAS benchmark and used emulation techniques to deploy and test VM in the cloud.…”

Section: Related Studiesmentioning

confidence: 99%

Evaluating ARM HPC clusters for scientific workloads

Maqbool

Fox

2015

Concurrency and Computation

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The power consumption of modern high-performance computing (HPC) systems that are built using power hungry commodity servers is one of the major hurdles for achieving Exascale computation. Several efforts have been made by the HPC community to encourage the use of low-powered system-on-chip (SoC) embedded processors in large-scale HPC systems. These initiatives have successfully demonstrated the use of ARM SoCs in HPC systems, but there is still a need to analyze the viability of these systems for HPC platforms before a case can be made for Exascale computation. The major shortcomings of current ARM-HPC evaluations include a lack of detailed insights about performance levels on distributed multicore systems and performance levels for benchmarking in large-scale applications running on HPC. In this paper, we present a comprehensive evaluation of results that covers major aspects of server and HPC benchmarking for ARMbased SoCs. For the experiments, we built an unconventional cluster of ARM Cortex-A9s that is referred to as Weiser and ran single-node benchmarks (STREAM, Sysbench, and PARSEC) and multi-node scientific benchmarks (High-performance Linpack (HPL), NASA Advanced Supercomputing (NAS) Parallel Benchmark, and Gadget-2) in order to provide a baseline for performance limitations of the system. Based on the experimental results, we claim that the performance of ARM SoCs depends heavily on the memory bandwidth, network latency, application class, workload type, and support for compiler optimizations. During server-based benchmarking, we observed that when performing memory intensive benchmarks for database transactions, x86 performed 12% better for multithreaded query processing. However, ARM performed four times better for performance to power ratios for a single core and 2.6 times better on four cores. We noticed that emulated double precision floating point in Java resulted in three to four times slower performance as compared with the performance in C for CPU-bound benchmarks. Even though Intel x86 performed slightly better in computation-oriented applications, ARM showed better scalability in I/O bound applications for shared memory benchmarks. We incorporated the support for ARM in the MPJ-Express runtime and performed comparative analysis of two widely used message passing libraries. We obtained similar results for network bandwidth, large-scale application scaling, floating-point performance, and energy-efficiency for clusters in message passing evaluations (NBP and Gadget 2 with MPJ-Express and MPICH). Our findings can be used to evaluate the energy efficiency of ARM-based clusters for server workloads and scientific workloads and to provide a guideline for building energy-efficient HPC clusters.

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Towards Fault-Tolerant Energy-Efficient High Performance Computing in the Cloud

Cited by 10 publications

References 10 publications

Adaptive time-based coordinated checkpointing for cloud computing workfl ows

Adaptive time-based coordinated checkpointing for cloud computing workfl ows

Smart scene management for IoT-based constrained devices using checkpointing

Evaluating ARM HPC clusters for scientific workloads

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