Towards formal verification of cryptographic circuits: A functional approach

Bitat, Abir; Merniz, Salah

doi:10.1109/pais.2018.8598527

Cited by 3 publications

(1 citation statement)

References 6 publications

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“…To verify the other versions of AES, with the appropriate changes in the behavioural and structural descriptions, the equivalence properties need to be explicit about two different sizes. When automatic verification is not possible, we can use the bottom-up proof method proposed in [27], where they started by verifying the functions (components) at the lowest level of the hierarchy, once they are verified, they replaced the implementation with its equivalent specification at the upper level, and so on until verifying the circuit.…”

Section: Formal Verification Of the Aes Circuitmentioning

confidence: 99%

Formal verification of pipelined cryptographic circuits: A functional approach

Bitat

Merniz

2021

IJCAI

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Cryptographic circuits are essential in systems where security is the main criteria. Therefore, it is crucial to ensure the correctness of not only the cryptographic algorithms, but also their hardware implementations. Formal methods, unlike the other validation techniques, guarantee the absence of errors.The problem is that designers still use conventional imperative Hardware Description Languages (HDLs), which are poorly suited for formal verification. This paper presents an automatic verification methodology for the pipelined cryptographic circuits using formal methods. It consists of using the functional HDL Lava to describe and verify the equivalence between the behavioural specification and structural implementation of a circuit. To the best of our knowledge, we are the first to use this functional HDL for that purpose. To show the features of the proposed approach, it was applied to verify the pipelined implementation of the cryptographic circuit AES (Advanced Encryption Standard).Povzetek: Za namene preverjanja formalne pravilnosti delovanja vezij je opisan funkcionalni pristop.

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Section: Formal Verification Of the Aes Circuitmentioning

confidence: 99%