Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits

Abstract

The cost of design, test and fabrication of self-timed circuits remains prohibitive for their wider adoption in practice. Addressing this issue, researchers are trying to find ways for rapid prototyping of self-timed circuits in FPGAs. Combinational logic is realized in FPGAs by look-up tables (LUTs), which are typically built as a binary tree of 2-way multiplexers (MUX 2:1). This brings us to the idea of using MUX 2:1 in self-timed designs particularly, in quasi-delay-insensitive (QDI) circuits. Multiplexers however, realize a binate (non-monotone) Boolean function and therefore may cause logic hazards. A standard way for preventing these hazards requires designing of special circuit for MUX 2:1. On the other hand, there are indirect evidences that the multiplexers in some commercial FPGAs are hazard-free. Based on this assumption, we propose an original approach for realizing a multi-input C-element, which is widely used in QDI circuits. This paves the way for using hazardfree MUX 2:1 in more complex self-timed elements. All the proposed circuits are designed and verified in a CAD tool Workcraft.

Signal Transition Graphs for Asynchronous Data Path Circuits

“…e initial speci cation for the method is the truth tables of Boolean (or multiple-valued) functions 6 . Based on the truth tables, we construct an STG for the module and map this STG into a circuit.…”

“…Fig. 6 shows two decompositions of the C-element [6], which have been veri ed under the environment in Fig. 5.…”