Towards layout-friendly high-level synthesis

Cong, Jason; Liu, Bin; Luo, Guojie; Prabhakar, Raghu

doi:10.1145/2160916.2160952

Cited by 17 publications

(5 citation statements)

References 41 publications

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“…Routing congestion can lead to timing violations, and lower power and area performance in the post-layout design phase [12]. Several methods have been proposed to adapt the HLS scheduling and allocation algorithms [13]- [16] to generate layout-friendly RTL models. For example, cut sizes and graph embedding metrics can correlate with routability, allowing one to evaluate the impact of HLS to improve the generated RTL routability on FPGA [16].…”

Section: Related Workmentioning

confidence: 99%

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs

et al. 2021

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Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While software developers can use high-level synthesis (HLS) to speed up registertransfer level (RTL) code generation from C++ or OpenCL source code, placement and routing issues, such as congestion, can still prevent achieving an FPGA programming bitstream or dramatically reduce the FPGA implementation performance. Congestion reports from physical design tools refer to thousands of RTL signal names instead of developer-accessible identifiers and statements, considerably complicating the developer understanding and resolution of the issues at the source level. We propose a high-level back-annotation flow that summarizes the routing congestion issues at the source level by analyzing the reports from the FPGA physical design tools and the internal debugging files of the HLS tools. Our flow describes congestion using comments back-annotated on the source code and identifies if the congestion causes are the on-chip memories or the DSP units (multipliers/adders), which are the shared resources very often associated with routing problems on FPGAs. We demonstrate on realistic large designs how the information provided by our flow helps to quickly spot congestion causes at the source level and to solve them using appropriate HLS directives.

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Section: Related Workmentioning

confidence: 99%

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs

et al. 2021

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“…However, as the abstraction level increases, the difficulty of congestion estimation is exacerbated due to the lack of physical information. Several HLS-based methods [8]- [11] are proposed to improve HLS scheduling or allocation algorithms to generate layout-friendly RTL models. [8]- [10] incorporate floorplanning to HLS and [11] summarizes multiple RTL metrics to evaluate the quality of HLS-generated models.…”

Section: Introductionmentioning

confidence: 99%

“…Several HLS-based methods [8]- [11] are proposed to improve HLS scheduling or allocation algorithms to generate layout-friendly RTL models. [8]- [10] incorporate floorplanning to HLS and [11] summarizes multiple RTL metrics to evaluate the quality of HLS-generated models. All of these methods aim at improving HLS algorithms, which is different from our problem that how to detect and eliminate congestion issues in the source code.…”

Section: Introductionmentioning

confidence: 99%

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

Zhao

Liang

Sinha

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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High-level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction level. Optimization of complex applications in HLS is challenging due to the effects of implementation issues such as routing congestion. Routing congestion estimation is absent or inaccurate in existing HLS design methods and tools. Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation. However, routability, a serious concern in FPGA designs, has been difficult to evaluate in HLS without analyzing post-implementation details after Place and Route. To this end, we propose a novel method to predict routing congestion in HLS using machine learning and map the expected congested regions in the design to the relevant high-level source code. This is greatly beneficial in early identification of routability oriented bottlenecks in the high-level source code without running timeconsuming register-transfer level (RTL) implementation flow. Experiments demonstrate that our approach accurately estimates vertical and horizontal routing congestion with errors of 6.71% and 10.05% respectively. By presenting Face Detection application as a case study, we show that by discovering the bottlenecks in high-level source code, routing congestion can be easily and quickly resolved compared to the efforts involved in RTL level implementation and design feedback.

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“…When running logic synthesis it may be too hard (or impossible) to resolve the congestion introduced by logic designers or HLS tools. To address this issue physically aware HLS approaches have been proposed to improve the congestion by changing the register/resource allocation or scheduling [1] [2][4] [6][8] [9] [10]. J. Cong and et al [3] propose a method of structural metrics called spreading score to handle the congestion problem at the HLS phase.…”

Section: Introductionmentioning

confidence: 99%

Physically aware high level synthesis design flow

Tatsuoka

Watanabe

Otsuka

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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High Level Synthesis (HLS) has many productivity advantages over traditional RTL design, but routing congestion is difficult to resolve due to the lack of physical information in HLS. In this paper we propose a novel design flow by integrating a HLS tool with physically aware logic synthesis technology. Using this approach, one can discover congestion problems early and trace their sources to specific parts of the input SystemC models. This allows designers to resolve the congestion problems before going to the layout design phase. We applied this flow to a large-scale HLS production design with results showing that this flow can significantly improve not only routing congestion but design area and timing as well.

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Towards layout-friendly high-level synthesis

Cited by 17 publications

References 41 publications

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

Physically aware high level synthesis design flow

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