Towards Machine Learning on the Automata Processor

Tracy, Tommy; Fu, Yao; Roy, Indranil; Jonas, Eric; Glendenning, Paul

doi:10.1007/978-3-319-41321-1_11

Cited by 50 publications

(25 citation statements)

References 12 publications

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“…Forest application, there are 1,661 reporting states corresponding to 10 feature classifications [6]. The host CPU post-processes this report data, so all of it must be preserved.…”

Section: Reporting Architecture (Match Output Offloading)mentioning

confidence: 99%

“…The Random Forest ("RF") kernel in the ANMLZoo benchmark suite is trained for the MNIST hand-writing database for digits 0-9 [6], so only four bits are necessary to encode the vote per cycle. However, because the minimum word width of SDAccel is 8 bits (one byte), we set the vote output the maximum number on our selected chip (1,156) in the absence of a general-purpose report-offloading architecture.…”

Section: 61gb 10gbpsmentioning

confidence: 99%

“…For decades, automata have faithfully served high-profile applications in domains such as deep packet inspection [3] [4] and antivirus file scanning [5] solely for the purpose of string pattern matching. However, recent research efforts have shown that automata processing can benefit other domains as well, including machine learning [6], pattern mining [7], bioinformatics [8], and even particle physics [9].…”

Section: Introductionmentioning

confidence: 99%

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FPGA Automata Processing

Xie

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Dwindling inter-generational CPU performance and power consumption improvements previously made possible by semiconductor scaling motivate hardware specialization for a wide variety of tasks. In recent years, implementing certain algorithms as specialized circuits ("accelerators") has been proven to improve both speediness and power/energy efficiency compared to the equivalent CPU implementation. One particular domain that shows great promise for hardware specialization is automata processing. Finite automata are most commonly known as the back-end data structures for regular expressions, which are used in a wide variety of applications such as antivirus file scanning and packet payload inspection for network intrusion detection systems (NIDS). Several research efforts have extended the applicability of finite automata beyond just regular expression into domains such as machine learning, particle physics, bioinformatics, and pattern mining. The versatility of automata processing as well as its inefficiency on traditional von Neumann computer architectures informs the need for a flexible and high-performance accelerator for these applications.In this thesis, an FPGA-based automata processing hardware accelerator is implemented in two different configurations: (1) a traditional discrete FPGA accelerator board attached over PCI-Express; and (2) a new tightly-coupled cache-coherent FPGA accelerator architecture utilizing the Intel Broadwell Xeon CPU + Arria 10 FPGA platform, known as the Hardware Accelerator Research Platform ("HARP").i

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“…Forest application, there are 1,661 reporting states corresponding to 10 feature classifications [6]. The host CPU post-processes this report data, so all of it must be preserved.…”

Section: Reporting Architecture (Match Output Offloading)mentioning

confidence: 99%

Section: 61gb 10gbpsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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FPGA Automata Processing

Xie

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“…There are a number of applications that have been explored on this processor, including machine learning [6], natural language processing [4], bioinformatics [5,22], high energy physics [20], and data analytics [23][24][25] itemsets in a database [24]. Searching for DNA motifs is another text-based application that found potential speed up in the AP [5,22].…”

Section: Applications On the Automata Processormentioning

confidence: 99%

“…It executes parallel processing of thousands of non-deterministic finite automata state machines that represent different regular expression patterns. This is ideal for pattern matching applications with large datasets, including Brill tagging, bioinformatics, and machine learning [4][5][6]. In [5], Roy et al designed a method on the automata to solve the DNA motif search problem and found speed-ups compared to conventional methods.…”

Section: Introductionmentioning

confidence: 99%

IP on AP: Exploring Image Processing on the Automata Processor

Ly¹

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The Automata Processor is a novel hardware accelerator that can perform pattern matching in parallel. To date, this pattern matching has been limited to one-dimensional problems that can be implemented as flexible string-matching methods such as those found in genomics. In this thesis, we present a novel process of implementing image retrieval using a multinary representation for deployment on an automata framework. Images are encoded into discriminative and unique regular expression descriptors in such a way that can be used for classification purposes. The regular expression descriptors are streamed through sets of non-deterministic finite automata (NFA).To improve performance of this multi-dimensional classification problem, we transform discriminative feature descriptors using a cumulative distribution transform. The transformed features are encoded into regular expressions which can be executed on the automata processor.The thesis also highlights methods of evaluating the similarity between images using these regular expressions in the automata processor. Our image retrieval and classification method improves on classification accuracy and achieves a run-time of less than one one-hundredth of a second per image which represents a three-fold improvement over competing architectures.i ACKNOWLEDGEMENTS

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Device and Circuit Architectures for In‐Memory Computing

Ielmini

Pedretti

2020

Advanced Intelligent Systems

120

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With the rise in artificial intelligence (AI), computing systems are facing new challenges related to the large amount of data and the increasing burden of communication between the memory and the processing unit. In‐memory computing (IMC) appears as a promising approach to suppress the memory bottleneck and enable higher parallelism of data processing, thanks to the memory array architecture. As a result, IMC shows a better throughput and lower energy consumption with respect to the conventional digital approach, not only for typical AI tasks, but also for general‐purpose problems such as constraint satisfaction problems (CSPs) and linear algebra. Herein, an overview of IMC is provided in terms of memory devices and circuit architectures. First, the memory device technologies adopted for IMC are summarized, focusing on both charge‐based memories and emerging devices relying on electrically induced material modification at the chemical or physical level. Then, the computational memory programming and the corresponding device nonidealities are described with reference to offline and online training of IMC circuits. Finally, array architectures for computing are reviewed, including typical architectures for neural network accelerators, content addressable memory (CAM), and novel circuit topologies for general‐purpose computing with low complexity.

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Towards Machine Learning on the Automata Processor

Cited by 50 publications

References 12 publications

FPGA Automata Processing

FPGA Automata Processing

IP on AP: Exploring Image Processing on the Automata Processor

Device and Circuit Architectures for In‐Memory Computing

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