Towards optimal use of pel decimation to trade off quality for energy

Squarer exploration for energy-efficient sum of squared differences

“…This difference can be decreased to ∼ 19.8% after applying clock gating. However, after simulation, the energy figures are almost identical between this work SSD and the SAD from [15]: while SAD uses 8.34 pJ/block, SSD requires only 8.30 pJ/block. One possible explanation is the use of two different versions of the synthesis tool.…”

“…The smallest reduction was for std (∼ 9.8%), while the largest was for and (∼ 14.4%), thus reducing their area difference to ∼ 17.4%. The SSD architecture using std squarer requires an area ∼ 97% larger than the SAD architecture presented in [15], synthesized for the same standard cell library and the same target throughput. Also, once the SAD architecture FSM from [15] is the same of the presented in this work (Figure 1(b)), the same frequency was used.…”

“…The SSD architecture using std squarer requires an area ∼ 97% larger than the SAD architecture presented in [15], synthesized for the same standard cell library and the same target throughput. Also, once the SAD architecture FSM from [15] is the same of the presented in this work (Figure 1(b)), the same frequency was used. The upper quadrants of Table I present power and energy/SSD 4×4 estimates obtained after the syntheses: the leftmost contains results of the syntheses without clock gating, while the rightmost presents the results where clock gating was applied.…”

“…According to the synthesis results prior to simulation, the std-SSD requires ∼ 50.1% higher energy than the SAD from [15]. This difference can be decreased to ∼ 19.8% after applying clock gating.…”

“…We assumed a target throughput of 16 million 4×4 blocks/s which is the same assumed in [15], necessary to encode full HD content (1920 × 1080) at 30 frames per second [16]. Therefore, the target period was set to 1.84 ns (∼ 543.47…”