Towards Practical Near-Maximum-Likelihood Decoding of Error-Correcting Codes: An Overview

Tonnellier, Thibaud; Hashemipour, Marzieh; Doan, Nghia; Gross, Warren J.; Balatsoukas‐Stimming, Alexios

doi:10.1109/icassp39728.2021.9414311

Cited by 10 publications

(3 citation statements)

References 34 publications

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“…Consequently, this results in a reduced effective information rate for the code and increased decoding complexity and latency. These challenges have increased attention towards codes and decoding algorithms specifically designed for short-length packets [7], [8], aiming to enhance communication performance and achieve low latency.…”

Section: Introductionmentioning

confidence: 99%

Pipelined Architecture for Soft-Decision Iterative Projection Aggregation Decoding for RM Codes

Hashemipour-Nazari,

Ren,

Goossens

et al. 2023

IEEE Trans. Circuits Syst. I

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Section: Introductionmentioning

confidence: 99%

Pipelined Architecture for Soft-Decision Iterative Projection Aggregation Decoding for RM Codes

Hashemipour-Nazari,

Ren,

Goossens

et al. 2023

IEEE Trans. Circuits Syst. I

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“…However, short packets make it challenging to achieve high reliability because conventional error-correcting schemes require large blocklengths to be effective. Therefore, renewed interest has been placed in decoding algorithms that specifically target short-length codes [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes

Hashemipour-Nazari

Goossens

Balatsoukas‐Stimming

2021

ICASSP 2021 - 2021 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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In this work, we present a simplification and a corresponding hardware architecture for hard-decision recursive projectionaggregation (RPA) decoding of Reed-Muller (RM) codes. In particular, we transform the recursive structure of RPA decoding into a simpler and iterative structure with minimal error-correction degradation. Our simulation results for RM(7, 3) show that the proposed simplification has a small error-correcting performance degradation (0.005 in terms of channel crossover probability) while reducing the average number of computations by up to 40%. In addition, we describe the first fully parallel hardware architecture for simplified RPA decoding. We present FPGA implementation results for an RM(6, 3) code on a Xilinx Virtex-7 FPGA showing that our proposed architecture achieves a throughput of 171 Mbps at a frequency of 80 MHz.

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“…As a result, GRAND can be used with any codebook, structured or unstructured. In comparison to other universal decoders, such as brute-force ML decoding and ordered statistic decoding (OSD) [16], GRAND provides a low complexity solution [17].…”

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confidence: 99%

High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND

Abbas,

Tonnellier,

Ercan

et al. 2021

Preprint

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Ultra-reliable low-latency communication (URLLC), a major 5G New-Radio use case, is the key enabler for applications with strict reliability and latency requirements. These applications necessitate the use of short-length and high-rate codes. Guessing Random Additive Noise Decoding (GRAND) is a recently proposed Maximum Likelihood (ML) decoding technique for these short-length and high-rate codes. Rather than decoding the received vector, GRAND tries to infer the noise that corrupted the transmitted codeword during transmission through the communication channel. As a result, GRAND can decode any code, structured or unstructured. GRAND has hardinput as well as soft-input variants. Among these variants, Ordered Reliability Bits GRAND (ORBGRAND) is a soft-input variant that outperforms hard-input GRAND and is suitable for parallel hardware implementation. This work reports the first hardware architecture for ORBGRAND, which achieves an average throughput of up to 42.5 Gbps for a code length of 128 at a target FER of 10 −7 . Furthermore, the proposed hardware can be used to decode any code as long as the length and rate constraints are met. In comparison to the GRANDAB, a hardinput variant of GRAND, the proposed architecture enhances decoding performance by at least 2 dB. When compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar (128, 105) code, the proposed ORBGRAND VLSI implementation has 49× higher average throughput, 32× times more energy efficiency, and 5× more area efficiency while maintaining similar decoding performance.

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Towards Practical Near-Maximum-Likelihood Decoding of Error-Correcting Codes: An Overview

Cited by 10 publications

References 34 publications

Pipelined Architecture for Soft-Decision Iterative Projection Aggregation Decoding for RM Codes

Pipelined Architecture for Soft-Decision Iterative Projection Aggregation Decoding for RM Codes

Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes

High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND

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