Towards Property Driven Hardware Security

Hu, Wei; Althoff, Alric; Ardeshiricham, Armaiti; Kastner, Ryan

doi:10.1109/mtv.2016.12

Cited by 26 publications

(15 citation statements)

References 22 publications

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“…Quantitative security properties allow more accurate measurement of hardware design security, e.g., assessing the severity of a vulnerability or evaluating the effectiveness of a security protection mechanism. Typical examples of such quantitative properties include randomness of the output of a cryptographic function [20], leakage of side and covert channels [39] and strength of a security mitigation [40]. These security properties are usually measured using statistical and information theoretic security metrics [41].…”

Section: F Quantitative Security Propertiesmentioning

confidence: 99%

“…This points to the need for any mitigation to come with proof that they are correct. Property driven hardware security [20] advocates for such an approach where the threat model is formally specified as properties, e.g., SystemVerilog Assertion (SVA) assertions, information flow properties, etc., and hardware security verification tools provide assurance that the designs adhere to the specified properties.…”

Section: B System and Architectural Protection Techniquesmentioning

confidence: 99%

“…Abstract properties are specified from the system-level and refined along the design process in order to provide a formal relationship between an abstract system model and its concrete implementation at the RTL. In a property driven solution to hardware security [20], high-level security specification is translated to lower level security policy, property, assertion and constraints in order to allow security to be formally verified on more concrete design models. This is demonstrated by a property specific approach to information flow security verification [295].…”

Section: B Security Driven Hardware Design Toolsmentioning

confidence: 99%

“…Proactive hardware information flow analyses facilitate vulnerability shielding and on-site monitoring. For example, unintentional hardware flaws and potential security vulnerabilities can be detected early by the recent security-driven hardware design flow [20]- [22]. As the rally of attacks and countermeasures is a neverending recursion, it is important to keep abreast of its latest development to continuously close the productivity gap of secure hardware design.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Chang

Sengupta

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: F Quantitative Security Propertiesmentioning

confidence: 99%

Section: B System and Architectural Protection Techniquesmentioning

confidence: 99%

Section: B Security Driven Hardware Design Toolsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Chang

Sengupta

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…Property driven hardware security. There has lately been a call for "property driven hardware security" [28], [29], [30] that advocates building security specifications into the hardware design workflow, automating the process of doing so, and developing quantifiable measures of security. We see Transys as a contribution in response to this call.…”

Section: Related Workmentioning

confidence: 99%

Transys: Leveraging Common Security Properties Across Hardware Designs

Zhang

Sturton

2020

2020 IEEE Symposium on Security and Privacy (SP)

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This paper presents Transys, a tool for translating security critical properties written for one hardware design to analogous properties suitable for a second design. Transys works in three passes adjusting the variable names, arithmetic expressions, logical preconditions, and timing constraints of the original property to retain the intended semantics of the property while making it valid for the second design. We evaluate Transys by translating 27 assertions written in a temporal logic and 9 properties written for use with gate level information flow tracking across 38 AES designs, 3 RSA designs, and 5 RISC processor designs. Transys successfully translates 96% of the properties. Among these, the translation of 23 (64%) of the properties achieved a semantic equivalence rate of above 60%. The average translation time per property is about 70 seconds.

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Integrating Information Flow Tracking into High-Level Synthesis Design Flow

Ardeshiricham

et al. 2021

Behavioral Synthesis for Hardware Security

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High-level synthesis (HLS) enables hardware designers to write an untimed circuit description allowing them to focus on architectural design optimizations like pipelining, task level parallelism, and array partitioning [1]. By removing the burden of describing cycle accurate behaviors, HLS designers can perform a more comprehensive design space exploration to better find an architecture that meets the desired power, performance, and area (PPA) constraints.While HLS tools are effective at exploring tradeoffs and optimizations related to PPA, security has largely been an after-thought. The emergence of hardware security flaws and threats [2-5] has brought a demand for hardware security verification tools. Due to the high cost (or even technical impossibility) to patch hardware security vulnerabilities after chip fabrication, identifying and eliminating security flaws in the early design phase is crucial.Information flow tracking (IFT) is a fundamental technique for hardware security verification [6][7][8]. IFT allows the designer to verify security properties related to confidentiality, integrity, and availability. An important first step is to create security enhanced circuit models for accurate description of security-related design behaviors and formal verification of security properties [9][10][11][12]. Some recent

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Towards Property Driven Hardware Security

Cited by 26 publications

References 22 publications

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Transys: Leveraging Common Security Properties Across Hardware Designs

Integrating Information Flow Tracking into High-Level Synthesis Design Flow

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