Towards real-time and real-life image classification and detection using CNN: a review of practical applications requirements, algorithms, hardware and current trends

Ilas, Mariana Eugenia; Ilas, C.

doi:10.1109/siitme50350.2020.9292253

Cited by 2 publications

(1 citation statement)

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“…Many more could benefit from edge ML in the future [16,17]. An overview of ML applications that are feasible on current hardware platforms is summarized in [18], illustrating the challenge of the limited edge processing power budget (<1W).…”

Section: Introductionmentioning

confidence: 99%

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Jokic¹,

Azarkhish²,

Bonetti³

et al. 2022

ACM Trans. Embed. Comput. Syst.

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Implementing embedded neural network processing at the edge requires efficient hardware acceleration that combines high computational throughput with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly being adapted to support the improved functionalities. Hardware designers can refer to a myriad of accelerator implementations in the literature to evaluate and compare hardware design choices. However, the sheer number of publications and their diverse optimization directions hinder an effective assessment. Existing surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effects of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. In contrast to previous surveys, this work provides a quantitative overview of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. The list of optimizations and their quantitative effects are presented as a construction kit, allowing to assess the design choices for each building block individually. Reported optimizations range from up to 10’000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators.

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Section: Introductionmentioning

confidence: 99%