Towards Schottky-barrier source/drain MOSFETs

Abstract

Section 3. Section 4 discusses device performance and noise behavior. This paper provides an overview of metal source/drain (SID) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, Le., extremely low source/drain resistance, sharp junctions from SID to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of silicide growth. Device design factors such as SID to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. In the past two years several groups have demonstrated high-performance SB MOSFETs, which places the technology as a promising candidate for future generations of CMOS technology.

Development of Schottky barrier field-effect transistors (SB-MOSFET) with ultra-low thermal budget

“…However, these fast transistors require rather complex processing steps with high thermal budgets, complex device architectures or even the introduction of additional terminals aimed to better control charge transport phenomena at the cost of increasing total power consumption [5][6][7], just like the additional 'Schottky bias' terminal in a MOSFET able to reach a subthreshold slope of 6 mV/dec [8]. Nevertheless, compared to conventional planar MOSFETs, more advantages in Schottky-barrier MOSFET devices like the low parasitic S/D resistance, low-temperature processing for S/D formation, elimination of parasitic bipolar action, inherent physical scalability to sub 10 nm gate length dimensions (due to the low resistance of the metal and the atomically abrupt junctions formed at a metal/silicon interface) [9], the choice of refractory metals for increased resistance to atomic diffusion trough the passivation layer and into the silicon substrate [10], etc, highlight the potential of a simple device able to show high performance with a low-cost and CMOS-compatible process. Moreover, a proper control on the Schottkybarrier height (SBH) of metal/semiconductor interfaces, could lead to applying well controlled Schottky-barrier contacts in advanced electron devices like the atomristor and other devices based on 2D materials [11,12].…”

Low temperature passivation of silicon surfaces for enhanced performance of Schottky-barrier MOSFET

“…Even though there have been immediate solutions to minimize Fermi level pinning at metal/semiconductor interfaces (mainly by the introduction of ultra-thin high-dielectric constant metal oxides [27]), these solutions complicate the transistor processing while increasing its total thermal budget, thus preventing introduction of these devices in advanced BEOL stages of an integrated circuit [27]. Nevertheless, compared to conventional planar MOSFETs, more advantages in Schottky-barrier MOSFET devices like the low parasitic S/D resistance, low-temperature processing for S/D formation, elimination of parasitic bipolar action, inherent physical scalability to sub 10 nm gate length dimensions (due to the low resistance of the metal and the atomically abrupt junctions formed at a metal/silicon interface) [28], the choice of refractory metals for increased resistance to atomic diffusion trough the passivation layer and into the silicon substrate [29], etc, highlight the potential of a simple device able to show high performance with a low-cost and CMOS-compatible process.…”