By the progressive scaling of the feature size and power consumption in VLSI chips the part of energy dissipated due to information loss in irreversible computations will become a serious limitation in the near future. Quantum-dot cellular automata (QCA) is an emerging nanotechnology with extremely low energy dissipation which facilitates new computation paradigms such as reversible computing. In this paper a novel reversible full adder-subtractor circuit based on QCA is proposed. Our proposed design is implemented using only one layer and does not require any rotated cells which significantly improves the manufacturability of the design. In addition, it improves the cell count, area and total energy dissipation by almost 45% and 50% and 48%, respectively, as compared to the existing QCAbased single-layer and multilayer reversible full adders.Keywords: Quantum-dot Cellular Automata; Reversible computing; Full adder design; Single layer circuit; Energy dissipation analysis
IntroductionPower consumption is indeed the main concern in recent VLSI circuits. Due to the ever-increasing demands for portable electronic systems and the disproportionate growth of the semiconductor and battery manufacturing industries, increasing the operational time between each battery charge has become very curtail. In addition, the disproportionate scaling of the size of transistors and power supply voltage has led to many shortcomings such as high leakage currents and high power density, creating hot spots in CMOS chips. As a result, different computational paradigms using emerging nanotechnologies, addressing drastically small size and low power dissipation, should be considered. Reversible computing is one these computational paradigms which is realized by setting up a one-toone mapping between the input and output states of the circuit [1][2][3]. In 1973 Bennett proved that it is possible to eliminate power dissipation in a logic circuit if the circuit includes only reversible logic gates. Moreover, in 1961 Landauer demonstrated that each bit of information loss in an irreversible computation leads to kBTln2 joules dissipation of heat energy, where kB is Boltzmann constant and T is temperature. As a result, the energy required for a binary transition at room temperature (T=300 K) is at least 0.017 eV. However, if a computation is carried out in a reversible manner, this amount of energy would not inevitably dissipated and energy consumption would be beyond the kBTln2 limit. Although the power dissipation of the current CMOS circuits is much higher than kBTln2, in the near future with ultimate scaling of feature size and power consumption based on emerging nanotechnologies, this theoretical limit may become a major restriction [3]. Utilizing reversible computing in nanotechnology and quantum computing has become a quite interesting subject in recent years. Reversible computing, as a new paradigm for reducing physical