Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans Based on Evolvable Hardware

Abstract

Hardware Trojans (HTs) are malicious hardware components designed to leak confidential information or cause the chip/circuit on which they are integrated to malfunction during operation. When we deploy such hardware platforms for edge computing, FPGA-based implementations of Coarse-Grained Reconfigurable Array (CGRA) are also currently falling victim to HT insertion. However, for CGRA, an evolvable hardware (EHW) platform, which has the ability to dynamically change its configuration and behavioral characteristics based on inputs from the environment, provides us with a new way to mitigate HT attacks. In this regard, we investigate the feasibility of using EHW to mitigate HTs that disrupt normal functionality in CGRA in this paper. When it is determined that HT is inserted into certain processing elements (PEs), the array autonomously reconfigures the circuit structure based on an evolutionary algorithm (EA) to avoid the use of HT-infected (HT-I) PEs. We show that the proposed approach is applicable to: (1) hardware platforms that support coarse-grained reconfiguration; and (2) pure combinatorial circuits. In a simulation environment built in Python, this paper reports experimental results for two target evolutionary circuits and outlines the effectiveness of the proposed method.

Efficient design methodology for adaptive system based on direct bitstream evolution

“…Extract the specific information nsfr, frofs, 1stCW, 2ndCW from the PIP database firstly. Then the actual start frame address of the specific PIP, frame, is calculated according to (14).…”

“…Currently, EHW has two mainstream implementation techniques [8,9]: virtual reconfigurable circuit (VRC)-based evolution [10,11,12,13,14] and dynamic partial reconfiguration (DPR)-based evolution [15,16,17,18,19]. The VRC is a virtual reconfigurable hardware layer built on top of the FPGA fabric that composed of an array of processing elements (PEs), where each PE contains all the intended required functions along with certain inter-PE connectivity configuration.…”