Towards variation-aware system-level power estimation of DRAMs

Chandrasekar, Karthik; Weis, Christian; Åkesson, Benny; Wehn, Norbert; Goossens, Kees

doi:10.1145/2463209.2488762

Cited by 37 publications

(31 citation statements)

References 27 publications

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“…Table 3 shows the specifications of the selected devices. All devices are made by the same vendor, since this makes it more likely that consistent safety (σ) margins have been applied to the specifications in the data sheet to compensate for variation [28]. This is especially important for the IDD current measures we supply to the power model in Section 4.2, as it makes the evaluation across devices fairer.…”

Section: Discussionmentioning

confidence: 99%

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Goossens

Chandrasekar

Åkesson

et al. 2016

IEEE Trans. Comput.

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Abstract-Real-time safety-critical systems should provide hard bounds on an applications' performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers' performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options. This article introduces a generalized close-page memory command scheduling algorithm that uses a variable number of banks in parallel to serve a request. To reduce the schedule length for DDR4 memories, we exploit bank grouping through a pairwise bank-group interleaving scheme. The algorithm is evaluated using an ILP formulation, and provides schedules of optimal length for most of the considered LPDDR, DDR2, DDR3, LPDDR2, LPDDR3 and DDR4 devices. We derive the worst-case bandwidth, power and execution time for the same set of devices, and discuss the observed trade-offs and trends in the scheduler-configuration design space based on these metrics, across memory generations.

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Section: Discussionmentioning

confidence: 99%

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Goossens

Chandrasekar

Åkesson

et al. 2016

IEEE Trans. Comput.

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“…As timing parameters for HMC have yet to be publicly released, we use the information provided in prior work [69,89] to model the latencies. [155,197], Controller open-page policy, cache line interleaving [80,94,98,156,193] We integrate DRAMPower [16], an open-source DRAM power profiling tool, into Ramulator such that it can perform power profiling while Ramulator executes. To isolate the effects of DRAM behavior, we focus on the power consumed by DRAM instead of total system power.…”

Section: :8mentioning

confidence: 99%

Demystifying Complex Workload-DRAM Interactions

GhoseSaugata

LiTianshi

HajinazarNastaran

et al. 2019

Proc. ACM Meas. Anal. Comput. Syst.

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It has become increasingly difficult to understand the complex interactions between modern applications and main memory, composed of Dynamic Random Access Memory (DRAM) chips. Manufacturers are now selling and proposing many different types of DRAM, with each DRAM type catering to different needs (e.g., high throughput, low power, high memory density). At the same time, memory access patterns of prevalent and emerging applications are rapidly diverging, as these applications manipulate larger data sets in very different ways. As a result, the combined DRAM-workload behavior is often difficult to intuitively determine today, which can hinder memory optimizations in both hardware and software. In this work, we identify important families of workloads, as well as prevalent types of DRAM chips, and rigorously analyze the combined DRAM-workload behavior. To this end, we perform a comprehensive experimental study of the interaction between nine different DRAM types and 115 modern applications and multiprogrammed workloads. We draw 12 key observations from our characterization, enabled in part by our development of new metrics that take into account contention between memory requests due to hardware design. Notably, we find that (1) newer DRAM technologies such as DDR4 and HMC often do not outperform older technologies such as DDR3, due to higher access latencies and, also in the case of HMC, poor exploitation of locality; (2) there is no single memory type that can effectively cater to all of the components of a heterogeneous system (e.g., GDDR5 significantly outperforms other memories for multimedia acceleration, while HMC significantly outperforms other memories for network acceleration); and (3) there is still a strong need to lower DRAM latency, but unfortunately the current design trend of commodity DRAM is toward higher latencies to obtain other benefits. We hope that the trends we identify can drive optimizations in both hardware and software design. To aid further study, we open-source our extensively-modified simulator, as well as a benchmark suite containing our applications.

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“…To model accelerator local scratchpads, we build and characterize a variety of SRAM blocks through a commercial memory compiler in the same technology node. LLC power estimates are obtained from CACTI 7 [27], and DRAM power is modeled by DRAMPower [28], with timing and power parameters taken from a commercial LP-DDR4 product datasheet [29].…”

Section: Power and Area Modelingmentioning

confidence: 99%

SMAUG: End-to-End Full-Stack Simulation Infrastructure for Deep Learning Workloads

Xi,

Yao,

Bhardwaj

et al. 2019

Preprint

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In recent years, there has been tremendous advances in hardware acceleration of deep neural networks. However, most of the research has focused on optimizing accelerator microarchitecture for higher performance and energy efficiency on a per-layer basis. We find that for overall single-batch inference latency, the accelerator may only make up 25-40%, with the rest spent on data movement and in the deep learning software framework. Thus far, it has been very difficult to study end-to-end DNN performance during early stage design (before RTL is available) because there are no existing DNN frameworks that support end-to-end simulation with easy custom hardware accelerator integration. To address this gap in research infrastructure, we present SMAUG, the first DNN framework that is purpose-built for simulation of end-to-end deep learning applications. SMAUG offers researchers a wide range of capabilities for evaluating DNN workloads, from diverse network topologies to easy accelerator modeling and SoC integration. To demonstrate the power and value of SMAUG, we present case studies that show how we can optimize overall performance and energy efficiency for up to 1.8-5× speedup over a baseline system, without changing any part of the accelerator microarchitecture, as well as show how SMAUG can tune an SoC for a camerapowered deep learning pipeline.

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Towards variation-aware system-level power estimation of DRAMs

Cited by 37 publications

References 27 publications

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Demystifying Complex Workload-DRAM Interactions

SMAUG: End-to-End Full-Stack Simulation Infrastructure for Deep Learning Workloads

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