Towards Variation-Aware Test Methods

Abstract

Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE.

Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault Detection in RFCMOS Amplifiers

“…The drawback of OBIST is, however, that the test circuitry is subject to the same process, supply voltage and temperature (PVT) variation as the CUT; a problem which has been discussed in the context of other RF BIST approaches [41]- [45], but has not received much attention in OBT and OBIST literature [45]. Adaptive test strategies may be used to dynamically alter test parameters based on wafer or die properties [46]- [50], including at RF [51], and should be considered in an OBT test threshold selection evaluation. Temperature-aware adaptive testing has also been shown to improve test efficacy [49], [52], especially when combined in full PVT awareness [53] but has not been explored in an OBT or OBIST context for RFCMOS.…”

An Efficient Degraded Deductive Fault Simulator for Small-Delay Defects

“…Furthermore, the presence of small delays will cause the chips easier to aging and can be taken as an indication of early life failures [2,3]. Therefore, small delay defect (SDD) screening becomes increasingly important in IC test [4][5][6] or diagnosis [7,8].…”