Towards zero latency photonic switching in shared memory networks

Abstract

Optical networks on chip based on silicon photonics have been proposed to reduce latency and power consumption in future chip multiprocessors. However, high performance chip multiprocessors use a shared memory model, which generates large numbers of short messages, creating high arbitration latency overhead for photonic switching networks. In this paper, we explore techniques that intelligently use information from the memory hierarchy to predict communication in order to setup photonic circuits with reduced or eliminated arbitration latency. Firstly, we present a switch scheduling algorithm, which arbitrates on a per memory transaction basis and holds open photonic circuits to exploit temporal locality. We show that this can reduce the average arbitration latency overhead by 60% and eliminate arbitration latency altogether for up to 70% of memory transactions. We then demonstrate that this switch scheduling algorithm operating with a central photonic crossbar or Clos switch has significant energy efficiency benefits over arbitrationfree photonic networks such as single writer multiple reader networks. Finally, we demonstrate that cache miss prediction can be used to predict 86% of more complex memory transactions involving multiple nodes or main memory.

Exploiting silicon photonics for energy‐efficient heterogeneous parallel architectures

“…Madarbux et al [5] present a switch scheduling algorithm which arbitrates on a per memory transaction basis and holds open photonic circuits to exploit temporal locality, showing that this can reduce the average arbitration latency overhead and eliminate arbitration latency altogether for many of memory transactions.…”