TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

Abstract

Abstract-There are increasing concerns about possible malicious modifications of integrated circuits (ICs) used in critical applications. Such attacks are often referred to as hardware Trojans. While many techniques focus on hardware Trojan detection during IC testing, it is still possible for attacks to go undetected. Using a combination of new design techniques and new memory technologies, we present a new approach that detects a wide variety of hardware Trojans during IC testing and also during system operation in the field. Our approach can also prevent a wide variety of attacks during synthesis, place-and-route, and fabrication of ICs. It can be applied to any digital system, and can be tuned for both traditional and split-manufacturing methods. We demonstrate its applicability for both ASICs and FPGAs. Using fabricated test chips with Trojan emulation capabilities and also using simulations, we demonstrate: 1. The area and power costs of our approach can range between 7.4-165% and 0.07-60%, respectively, depending on the design and the attacks targeted; 2. The speed impact can be minimal (close to 0%); 3. Our approach can detect 99.998% of Trojans (emulated using test chips) that do not require detailed knowledge of the design being attacked; 4. Our approach can prevent 99.98% of specific attacks (simulated) that utilize detailed knowledge of the design being attacked (e.g., through reverse-engineering). 5. Our approach never produces any false positives, i.e., it does not report attacks when the IC operates correctly. I. INTRODUCTION HERE is growing concern about the trustworthiness of integrated circuits (ICs). If an untrusted party fabricates an IC, there is potential for an adversary to insert a malicious hardware Trojan [1], an unauthorized modification of the IC resulting in incorrect functionality and/or sensitive data being exposed [2]. These include (but are not limited to) [3]: a) Modification of functional behavior through logic changes: Index TermsFor example, extra logic gates may be inserted to force an incorrect logic value on a wire at some (arbitrary) point in time (Fig. 1a) [2]. b) Electrical modification: For example, extra capacitive loading may be placed on a circuit path to alter timing characteristics of the IC (Fig. 1b) [2]. c) Reliability degradation: For example, aging of transistors (e.g., Negative Bias Temperature Instability (NBTI)) may be accelerated, degrading reliability ( Fig. 1c) [4]. A hardware Trojan is detected when we report malicious modifications to an IC. A hardware Trojan is prevented when Manuscript received January 9, 2015; revised May 8, 2015; accepted July 20, 2015. Work supported by IARPA Trusted Integrated Chips (TIC) Program. All authors are with Dept. of Electrical Engineering, Stanford University, Stanford, CA 94305 USA (e-mail: tonyfwu@stanford.edu). S. Mitra is also with Dept. of Computer Science, Stanford University.we stop a hardware Trojan from being inserted. Part of the challenge in detecting or preventing hardware Trojans arises from the fact that...

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

“…8). Among other considerations, this suggests that any chip can only be considered trustworthy if all the individual hardware components as well as the whole (2D/3D) chip have been thoroughly evaluated in terms of their actual, implemented functionality versus their intended, specified functionality [116], [117], [118], [119] * 3 . One crucial concern here is the economics-driven trend to increasingly outsource various steps of the manufacturing flow, e.g., to outsourced semiconductor assembly and test (OSAT) parties [122].…”

“…We expect this trend to further intensify for the complex and diverse 3D integration landscape, thereby increasing the risk exposure for 3D chips. To address and manage this challenge of verification and other security-centric challenges, the notions of "secure by design" and "design-for-trust" have been promoted for some years now for "regular" 2D chips [116], [117], [118], [119], [123], [124], [125], [126], [127], [128]. Similar studies are recently focusing on 3D chips as well [129], [130], [131], [132], [133], [134], [135], [136], [137], [138].…”

“…Recent work on structural and functional verification targets the security analysis of outsourced components [116], [117], [118], [119]. In general, for any 2D/3D chip, the efforts for verification scale with: ( 1 ) the number of outsourced components; ( 2 ) the structural and functional complexity of the outsourced components; ( 3 ) the "permission for introspection" of outsourced components: soft IP components typically offer detailed insights and access into their implementation, whereas hard IP components tend to obfuscate such details; and ( 4 ) the system-level connectivity of outsourced components intertwined with custom-designed components.…”

“…The detection of hardware Trojans, both at design and runtime, has recently gained more interest, and promising techniques have been proposed [116], [117], [118], [119], [145], [148], [152], [153]. For example, simulation-based Trojan detection cannot guarantee full coverage within polynomial runtime, but Wei et al [153] demonstrate full coverage for industrial circuits within minutes by combining reverse engineering and formal verification.…”

Hardware Trojan Identification and Detection

“…However, this can increase the chip area and delay leading to reduced performance. Run-time monitoring approaches greatly improve chip reliability when trojans pass the test phase [19]. Another approach is to use self-destructive packaging to disable chips or discard the output when a trojan is detected.…”