TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation

Yan, Aibin; Liang, Ding; Shan, Chuanbo; Cai, Haidong; Chen, Xiaofeng; Wei, Zhanjun; Huang, Zhengfeng; Wen, Xiaoqing

doi:10.1109/iscas51556.2021.9401453

Cited by 11 publications

(4 citation statements)

References 22 publications

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“…In this section, the DICE [26], TPDICE-based D-latch [27], high performance SEU tolerant (HSPT) latch [28], DNUCT [29], LSEDUT D-latch [25], QNUTL-CG D-latch [7], 4NUHL latch [30], and the proposed D-latch are simulated at 0.8 V supply voltage and 250 MHz frequencies at room temperature using Synopsys R HSPICE in 22 nm PTM technology. In this simulation, PMOS transistors have an aspect ratio W/L = 35 nm/22 nm, and NMOS transistors have an aspect ratio W/L = 24 nm/22 nm.…”

Section: Simulationmentioning

confidence: 99%

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

et al. 2022

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As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in harsh radiative environments. In this manuscript, a new high reliable D-latch which can tolerate quadruple-node upsets is presented. The design is based on a low-cost single event double-upset tolerant (LSEDUT) cell and a clock-gating triple-level soft-error interceptive module (CG-SIM). Due to its LSEDUT base, it can tolerate two upsets, but the combination of two LSEDUTs and the triple-level CG-SIM provides the proposed D-latch with remarkable quadruple-node upsets (QNU) tolerance. Applying LSEDUTs for designing a QNU-tolerant D-latch improves considerably its features; in particular, this approach enhances its reliability against process variations, such as threshold voltage and (W/L) transistor variability, compared to previous QNU-tolerant D-latches and double-node-upset tolerant latches. Furthermore, the proposed D-latch not only tolerates QNUs, but it also features a clear advantage in comparison with the previous clock gating-based quadruple-node-upset-tolerant (QNUTL-CG) D-latch: it can mask single event transients. Specific figures of merit endorse the gains introduced by the new design: compared with the QNUTL-CG D-latch, the improvements of the maximum standard deviations of the gate delay, induced by threshold voltage and (W/L) transistors variability of the proposed D-latch, are 13.8% and 5.7%, respectively. Also, the proposed D-latch has 23% lesser maximum standard deviation in power consumption, resulting from threshold voltage variability, when compared to the QNUTL-CG D-latch.INDEX TERMS Power-delay product (PDP), soft errors (SE), single event upset (SEU), high impedance state (HIS), single event transient (SET), dual interlocked storage cell (DICE), triple path DICE (TPDICE), quadruple-node upsets (QNUs).

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Section: Simulationmentioning

confidence: 99%

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

et al. 2022

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“…Clearly, among the existing latch circuits, there are some SNU-mitigated ones [12], [13], [14], there are some both SNU-and DNU-mitigated ones [15], [16], [17], [18], [19], [25], [26], [27], [28], [29], and there are also some SNU, DNU, and TNU simultaneously mitigated ones [20], [21], [22], [23], [24]. As far as we know, there are only a few latches that are hardened against SNUs, DNUs, TNUs, and QNUs, simultaneously [4], [5], [24], [30], [31]. However, these latches cannot self-recover from QNUs or suffer from large overhead in terms of power, delay, and/or area.…”

Section: Introductionmentioning

confidence: 99%

“…To protect against soft errors for storage elements, researchers in recent years have proposed many designs of SRAM cells [7], [8], flip-flops [1], [9], [10], [11] as well as latches [4], [5], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31]. Clearly, among the existing latch circuits, there are some SNU-mitigated ones [12], [13], [14], there are some both SNU-and DNU-mitigated ones [15], [16], [17], [18], [19], [25], [26], [27], [28], [29], and there are also some SNU, DNU, and TNU simultaneously mitigated ones [20], [21], [22], [23], [24].…”

Section: Introductionmentioning

confidence: 99%

Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments

Yan

Cui

et al. 2023

IEEE Trans. Aerosp. Electron. Syst.

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This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low-cost version of the QRHIL), for highly robust computing in harsh radiation environments. First, the QRHIL that mainly consists of a 5×5 looped C-element matrix is proposed. Then, to reduce overhead, the QRHIL-LC that mainly uses 24 interlocking C-elements is proposed. Both latches can self-recover from any QNU, while the QRHIL-LC has a low cost compared to the QRHIL. Simulation waveforms show the QNU-recoverability of the proposed QRHIL and QRHIL-LC latches. Moreover, compared with the QRHIL latch, the QRHIL-LC can approximately save power dissipation by 16% and silicon area by 5%.

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“…To tolerate soft errors in the device level, many storage cells, such as latches [2][3][4][5][6][7][8][9][10][11][12], SRAMs [13][14], and flip-flops [15][16], have been proposed. This paper focuses on latch designs.…”

Section: Introductionmentioning

confidence: 99%

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

Yan

Cui

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to chargesharing-induced multiple-node-upsets (MNUs) in harsh radiation environments. Muller C-elements are widely used for latch hardening against MNUs, such as triple and even quadruple node-upsets. Existing latch verifications for error-recovery highly rely on EDA tools with complex error-injection combinations. In this paper, a latch design with algorithm-based verification protected against MNUs in harsh radiation environments, is proposed. Due to the formed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification results demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing same-type design.

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TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation

Cited by 11 publications

References 22 publications

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

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