Trace-driven HW/SW cosimulation using virtual synchronization technique

Kim, Dohyung; Yi, Youngmin; Ha, Soonhoi

doi:10.1145/1065579.1065669

Cited by 28 publications

(18 citation statements)

References 5 publications

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“…As shown in Thompson et al [36], the performance overhead caused by wrappers and time synchronizations is in that case reduced to a minimum. Our on-line calibration technique shows some similarities with the trace-driven co-simulation technique in Kim et al [23]. However, the latter operates at a lower abstraction level and is applied in a classical HW/ SW co-simulation context.…”

Section: Related Workmentioning

confidence: 97%

“…E.g., system-level cosimulations with cycle-accurate components are typically synchronized at cycle granularity, causing high performance overheads. Besides the performance overheads caused by wrappers and time synchronization, the IPC mechanisms often used for communication between the co-simulation components may also severely limit performance [23], especially when synchronizing at cycle granularity.…”

Section: Related Workmentioning

confidence: 99%

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Calibration of Abstract Performance Models for System-Level Design Space Exploration

Pimentel

Thompson

Polstra

et al. 2007

J Sign Process Syst Sign Image

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Abstract. High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such highlevel modeling and simulation methods is that they should yield trustworthy performance estimations. This requires validation (if possible) and calibration of the simulation models, which are two aspects that have not yet been widely addressed in the system-level community. This article presents a number of mechanisms for both calibrating isolated model components as well as a system-level performance model as a whole. We discuss these model calibration mechanisms in the context of our Sesame system-level simulation framework. Two illustrative case studies will also be presented to indicate the merits of model calibration.

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Section: Related Workmentioning

confidence: 97%

Section: Related Workmentioning

confidence: 99%

Calibration of Abstract Performance Models for System-Level Design Space Exploration

Pimentel

Thompson

Polstra

et al. 2007

J Sign Process Syst Sign Image

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show abstract

“…"Virtual Synchronization" [Yi et al 2003;Kim et al 2005] aims to reduce the overhead of synchronizing component clocks in distributed HW/SW cosimulation. The overhead of clock synchronization is similar to the scheduling overhead in MESH.…”

Section: Prior Work In Interrupt Modelingmentioning

confidence: 99%

Interrupt modeling for efficient high-level scheduler design space exploration

Johnson

Paul

2008

ACM Trans. Des. Autom. Electron. Syst.

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Single Chip Heterogeneous Multiprocessors executing a wide variety of software are increasingly common in consumer electronics. Because of the mix of real-time and best effort software across the entire chip, a key design element of these systems is the choice of scheduling strategy. Without task migration, the benefits of single chip processing cannot be fully realized. Previously, high-level modeling environments have not been capable of modeling asynchronous events such as interrupts and preemptive scheduling while preserving the performance benefits of high level simulation. This paper shows how extensions to Modeling Environment for Software and Hardware (MESH) enable precise modeling of these asynchronous events while running more than 1000 times faster than cycle-accurate simulation. We discuss how we achieved this and illustrate its use in modeling preemptive scheduling. We evaluate the potential of migrating running tasks between processors to improve performance in a multimedia cell phone example. We show that by allowing schedulers to rebalance processor loads as new tasks arrive significant performance gains can be achieved over statically partitioned and dynamic scheduling approaches. In our example, we show that system response time can be improved by as much as 1.96 times when a preemptive migratory scheduler is used, despite the overhead incurred by scheduling tasks across multiple processors and transferring state during the migration of running tasks. The contribution of this work is to provide a framework for evaluating preemptive scheduling policies and task migration in a high level simulator, by combining the new ability to model interrupts with dramatically increased efficiency in the high-level modeling of scheduling and commuincation MESH already provides.

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“…The virtual clock synchronization technique presented by Youngmin et al [17], [9] uses a very similar approach to speed up simulations.…”

Section: Related Workmentioning

confidence: 99%

A Heterogeneous Hardware-Software Co-Simulation Environment Using User Mode Linux and Clock Suppression

Muhr

Holler

Horauer

2006

2006 2nd IEEE/ASME International Conference on Mechatronics and Embedded Systems and Applications

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Abstract-With the ever increasing complexity of electronic systems and the fact that networked embedded systems become more and more widespread, substantial research has already been devoted to such issues as hardware-software co-design and co-verification, virtual prototypes, and heterogeneous simulation environments including instruction set simulators.The work presented herein, however, presents a new and efficient heterogeneous hardware-software co-simulation environment for network or communication centric distributed embedded systems. It is new, since for the first time it integrates a complete operating system kernel and thus enables testing of driver software and protocol stacks. It is efficient, since it allows intelligently turning off unnecessary simulation loads to allow for the long simulation run times typically needed for communication protocol simulation.The correctness and validity of this virtual prototyping approach are shown by comparing simulation results with reallife measurements in a prototype system developed with the presented simulation environment.

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Trace-driven HW/SW cosimulation using virtual synchronization technique

Cited by 28 publications

References 5 publications

Calibration of Abstract Performance Models for System-Level Design Space Exploration

Calibration of Abstract Performance Models for System-Level Design Space Exploration

Interrupt modeling for efficient high-level scheduler design space exploration

A Heterogeneous Hardware-Software Co-Simulation Environment Using User Mode Linux and Clock Suppression

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